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A/D采样控制模块设计 A/D采样控制模块负责控制外部ADC0809芯片多路模拟输入量的选通以及实现对A/D采样过程的合理控制。此部分的设计根据《EDA技术与VHDL》P211——P212的例8

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
  PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       CLK:IN STD_LOGIC;
       EOC:IN STD_LOGIC;
       EN:IN STD_LOGIC;
       ALE:OUT STD_LOGIC;
       START:OUT STD_LOGIC;
       OE:OUT STD_LOGIC;
       ADDA:OUT STD_LOGIC;
       LOCK0:OUT STD_LOGIC;
      Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ADCINT;
ARCHITECTURE ONE OF ADCINT IS
TYPE states IS (st0,st1,st2,st3,st4);   
  SIGNAL current_state,next_state:states:=st0;
  SIGNAL REGL:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LOCK:STD_LOGIC;
 BEGIN
  ADDA <=EN;
  Q<=REGL;LOCK0<=LOCK;
    COM:PROCESS(current_state,EOC) BEGIN
     CASE current_state IS
      WHEN st0=>ALE<='0';START<='0';LOCK<='0';OE<='0';
            next_state<=st1;
       WHEN st1=>ALE<='1';START<='1';LOCK<='0';OE<='0';
            next_state<=st2;
       WHEN st2=>ALE<='0';START<='0';LOCK<='0';OE<='0';
            IF(EOC='1') THEN next_state<=st3;
             ELSE next_state<=st2;END IF;
       WHEN st3=>ALE<='0';START<='0';LOCK<='0';OE<='1';
            next_state<=st4;
       WHEN st4=>ALE<='0';START<='0';LOCK<='1';OE<='1';next_state<=st0;
       WHEN OTHERS=>next_state<=st0;
       END CASE;
     END PROCESS COM;
      REG:PROCESS(CLK)
         BEGIN
          IF(CLK'EVENT AND CLK='1') THEN current_state<=next_state;END IF;
      END PROCESS REG;
      LATCH1:PROCESS(LOCK)
          BEGIN
            IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;END IF;
      END PROCESS LATCH1;
END ONE;