sdram_ctrl.vhd

同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用

				end if;   
				when INIT1=>operation<=INIT2;
				when INIT2=>operation<=INIT3;
				when INIT3=>operation<=INIT4;
				when INIT4=>operation<=INIT5;
				when INIT5=>operation<=INIT6;
				when INIT6=>operation<=INIT7;
				when INIT7=>operation<=INIT8;
				when INIT8=>operation<=INIT9;
				when INIT9=>operation<=INIT10;
				when INIT10=>operation<=INIT11;
				when INIT11=>operation<=INIT12;
				when INIT12=>operation<=INIT13;	
				when INIT13=>operation<=INIT14;
				when INIT14=>operation<=INIT15;
				when INIT15=>operation<=INIT16;
				when INIT16=>operation<=INIT17;
				when INIT17=>operation<=INIT18;
				when INIT18=>operation<=INIT19;
				when INIT19=>operation<=INIT20;
				when INIT20=>operation<=INIT21;
				when INIT21=>operation<=INIT22;
				when INIT22=>operation<=INIT23;
				when INIT23=>operation<=INIT24;row<=MODE((row'length-1) downto 0);
				when INIT24=>operation<=IDLE;	
				
				when REFRESH0=>operation<=REFRESH1;		 
				when REFRESH1=>operation<=REFRESH2;	 
				when REFRESH2=>operation<=REFRESH3; 
				when REFRESH3=>operation<=REFRESH4;	 
				when REFRESH4=>operation<=REFRESH5;	 
				when REFRESH5=>operation<=REFRESH6;	 
				when REFRESH6=>operation<=REFRESH7;	 
				when REFRESH7=>operation<=REFRESH8;	 
				when REFRESH8=>operation<=REFRESH9;
				when REFRESH9=>operation<=REFRESH10;	 
				when REFRESH10=>operation<=REFRESH11;
				when REFRESH11=>operation<=REFRESH12;
				when REFRESH12=>operation<=REFRESH13;
				active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
				when REFRESH13=>operation<=REFRESH14;	
				when REFRESH14=>operation<=IDLE;          	
				
				when ACTIVE0=>operation<=ACTIVE1;	 
				when ACTIVE1=>operation<=ACTIVE2;	  
				when ACTIVE2=>operation<=ACTIVE3;	
				active_address<=unsigned(fifo_q((fifo_q'length-1) downto (fifo_q'length-bank'length-row'length)));
				when ACTIVE3=>operation<=ACTIVE4;
				when ACTIVE4=>operation<=IDLE;    	   
				
				when others=>  
				if do_refresh='1'
					then
					if tRCD_not_expired='0' and operation=IDLE
						then operation<=REFRESH0;row(10)<='1';
					else operation<=IDLE;
					end if;	
				elsif do_active='1'
					then
					if tRCD_not_expired='0' and operation=IDLE	
						then operation<=ACTIVE0;row(10)<='1';
					else operation<=IDLE;
					end if;	
				elsif fifo_empty='1'
					then
					operation<=IDLE;	
				elsif fifo_q(1)='1' --write
					then  
					if read_latency(CAS_LATENCY-1 downto 0)>"000"
						then operation<=IDLE;
					else operation<=WRITE0; 
					end if;	
				elsif fifo_q(0)='1'	--read
					then
					operation<=READ0;
				end if;	
			end case;
		end if;	
	end process;  			
	
	control_latency:process(reset,clk)
	begin
		if reset='1'
			then 
			read_latency<=(others=>'0');
		elsif rising_edge(clk)
			then 
			read_latency<=std_logic_vector(unsigned(read_latency) SLL 1);
			if operation=READ0
				then read_latency(0)<='1';
			else read_latency(0)<='0';	
			end if;	
		end if;	
	end process; 	 
	latch_readdata:process(reset,clk)
	begin
		if reset='1'
			then
			avs_nios_readdata<=(others=>'0');
			avs_nios_readdatavalid<='0';
		elsif rising_edge(clk)
			then
			avs_nios_readdata<=sdram_dq;
			avs_nios_readdatavalid<=read_latency(CAS_LATENCY);
		end if;	
	end process;
	initialization:process(reset,clk)
	begin
		if rising_edge(clk)
			then	
			if init_counter>0
				then
				init_counter<=init_counter-1; 
			else do_init<='1';	
			end if;
		end if;	
	end process;	
	refreshing:process(clk,reset)
	begin	 
		if reset='1'
			then
			refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);	
			do_refresh<='0';
		elsif rising_edge(clk)
			then						 
			if refresh_counter=to_unsigned(0,refresh_counter'length)
				then refresh_counter<=to_unsigned(REFRESH_PERIOD_CLOCKS,16);	
				do_refresh<='1';
			else refresh_counter<=refresh_counter-1;
			end if;
			if operation=REFRESH0 or operation=REFRESH5
				then do_refresh<='0';
			end if;
		end if;	
	end process;
	active_period:process(reset,clk)
	begin
		if reset='1'
			then
			active_counter<=(others=>'0');	
			tRCD_not_expired<='0';
		elsif rising_edge(clk)
			then	
			if operation=ACTIVE3 or operation=REFRESH13
				then active_counter<=to_unsigned(5,active_counter'length);
			elsif active_counter>0
				then active_counter<=active_counter-1;
			end if;	
		end if;
		if active_counter>0
			then tRCD_not_expired<='1';
		else tRCD_not_expired<='0';
		end if;	
	end process;  
	latch_controls:process(clk,reset)
	begin	 			
		if reset='1'
			then	 
			i_command<=NOP;
			i_address<=(others=>'0');
			i_bank<=(others=>'0');
			i_dqm<=(others=>'0');
			i_data<=(others=>'Z');
		elsif rising_edge(clk)
			then
			i_command<=NOP;
			i_bank<=bank;
			i_address<=(others=>'0');
			i_address((column'length-1) downto 0)<=column;
			i_data<=(others=>'Z');
			i_dqm<=(others=>'0'); 	   
			
			case operation is	
				when INIT1|REFRESH0|ACTIVE0 =>  
				i_command<=PRECHARGE;
				i_address<=row;
				when INIT4|INIT14|REFRESH3 =>   
				i_command<=AUTO_REFRESH;
				when INIT24=> 
				i_command<=LOAD_MODE_REGISTER;
				i_address<=row;
				when ACTIVE3|REFRESH13 => 
				i_command<=ACTIVE;
				i_address<=row;
				when READ0 =>
				i_command<=READ;
				when WRITE0 => 	
				i_command<=WRITE;
				i_dqm<=not be; 
				i_data<=data;
				when OTHERS => 
			end case;
		end if;
	end process;
	
	fifo: scfifo
	GENERIC MAP (
		add_ram_output_register => "ON",
		intended_device_family => "Cyclone",
		lpm_numwords => 4,
		lpm_showahead => "ON",
		lpm_type => "scfifo",
		lpm_width => FIFO_WIDTH,
		lpm_widthu => 2,
		overflow_checking => "ON",
		underflow_checking => "ON",
		use_eab => "ON"
		)
	PORT MAP (
		rdreq => fifo_rdreq,
		aclr => reset,
		clock => clk,
		wrreq => fifo_wrreq,
		data => fifo_data,
		empty => fifo_empty,
		q => fifo_q,
		full => fifo_wrfull
		);
end behaviour;