adder8b.txt

本程序是利用两个4位二进制并行加法器通过级联方式构成一个8位加法器。

程序（1）：4位加法器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4b is--4位二进制并行加法器
    port( cin:in std_logic;--低位进位
               a:in std_logic_vector(3 downto 0);  --4位加数
               b:in std_logic_vector(3 downto 0);--4位被加数
               s: out std_logic_vector(3 downto 0);--4位和
               cout: out std_logic);--进位输出
end adder4b;
architecture behav of adder4b is
signal sint:std_logic_vector(4 downto 0);
signal aa,bb:std_logic_vector(4 downto 0);
begin
aa<='0'&a;--将4位加数矢量扩为5位，为进位提供空间
bb<='0'&b;--将4位被加数矢量扩为5位，为进位提供空间
sint<=aa+bb+cin;
s<=sint(3 downto 0);
cout<=sint(4)l
end behav;
程序（2）：8位加法器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8b is
        port( cin:in std_logic;
                   a:in std_logic_vector(7 downto 0);
                   b:in std_logic_vector(7 downto 0);
                   s:out std_logic_vector(7 downto 0);
                  cout:out std_logic);
end adder8b ;
architecture struc of adder8b is
component adder4b is
      port(cin:in std_logic;
                a:in std_logic_vector(3 downto 0);
                b:in std_logic_vector(3 downto 0);
                 s:in out std_logic_vector(3 downto 0);
                cout:out std_logic);
end component;
signal carry_out :std_logic;
begin
    u1:adder4b
    port map(cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),
                     s=>s(3 downto 0),cout=>carry_out );
     u2:adder4b
     port map(cin=>carry_out,a=>a(7 downto 4),
                      b=>b(7 downto 4),s=>s(7 downto 4),cout=>cout);
end struc;