dds_vhdl.map.eqn

这个是相当不错的EDA编程

SB1_q_a[2]_PORT_B_write_enable = TB1L62;
SB1_q_a[2]_PORT_B_write_enable_reg = DFFE(SB1_q_a[2]_PORT_B_write_enable, SB1_q_a[2]_clock_1, , , );
SB1_q_a[2]_clock_0 = CLK;
SB1_q_a[2]_clock_1 = A1L5;
SB1_q_a[2]_PORT_A_data_out = MEMORY(SB1_q_a[2]_PORT_A_data_in_reg, SB1_q_a[2]_PORT_B_data_in_reg, SB1_q_a[2]_PORT_A_address_reg, SB1_q_a[2]_PORT_B_address_reg, SB1_q_a[2]_PORT_A_write_enable_reg, SB1_q_a[2]_PORT_B_write_enable_reg, , , SB1_q_a[2]_clock_0, SB1_q_a[2]_clock_1, , , , );
SB1_q_a[2] = SB1_q_a[2]_PORT_A_data_out[0];

--SB1_q_b[2] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[2]
SB1_q_b[2]_PORT_A_data_in = VCC;
SB1_q_b[2]_PORT_A_data_in_reg = DFFE(SB1_q_b[2]_PORT_A_data_in, SB1_q_b[2]_clock_0, , , );
SB1_q_b[2]_PORT_B_data_in = TB1_ram_rom_data_reg[2];
SB1_q_b[2]_PORT_B_data_in_reg = DFFE(SB1_q_b[2]_PORT_B_data_in, SB1_q_b[2]_clock_1, , , );
SB1_q_b[2]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_b[2]_PORT_A_address_reg = DFFE(SB1_q_b[2]_PORT_A_address, SB1_q_b[2]_clock_0, , , );
SB1_q_b[2]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[2]_PORT_B_address_reg = DFFE(SB1_q_b[2]_PORT_B_address, SB1_q_b[2]_clock_1, , , );
SB1_q_b[2]_PORT_A_write_enable = GND;
SB1_q_b[2]_PORT_A_write_enable_reg = DFFE(SB1_q_b[2]_PORT_A_write_enable, SB1_q_b[2]_clock_0, , , );
SB1_q_b[2]_PORT_B_write_enable = TB1L62;
SB1_q_b[2]_PORT_B_write_enable_reg = DFFE(SB1_q_b[2]_PORT_B_write_enable, SB1_q_b[2]_clock_1, , , );
SB1_q_b[2]_clock_0 = CLK;
SB1_q_b[2]_clock_1 = A1L5;
SB1_q_b[2]_PORT_B_data_out = MEMORY(SB1_q_b[2]_PORT_A_data_in_reg, SB1_q_b[2]_PORT_B_data_in_reg, SB1_q_b[2]_PORT_A_address_reg, SB1_q_b[2]_PORT_B_address_reg, SB1_q_b[2]_PORT_A_write_enable_reg, SB1_q_b[2]_PORT_B_write_enable_reg, , , SB1_q_b[2]_clock_0, SB1_q_b[2]_clock_1, , , , );
SB1_q_b[2] = SB1_q_b[2]_PORT_B_data_out[0];


--SB1_q_a[1] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[1]_PORT_A_data_in = VCC;
SB1_q_a[1]_PORT_A_data_in_reg = DFFE(SB1_q_a[1]_PORT_A_data_in, SB1_q_a[1]_clock_0, , , );
SB1_q_a[1]_PORT_B_data_in = TB1_ram_rom_data_reg[1];
SB1_q_a[1]_PORT_B_data_in_reg = DFFE(SB1_q_a[1]_PORT_B_data_in, SB1_q_a[1]_clock_1, , , );
SB1_q_a[1]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_a[1]_PORT_A_address_reg = DFFE(SB1_q_a[1]_PORT_A_address, SB1_q_a[1]_clock_0, , , );
SB1_q_a[1]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_a[1]_PORT_B_address_reg = DFFE(SB1_q_a[1]_PORT_B_address, SB1_q_a[1]_clock_1, , , );
SB1_q_a[1]_PORT_A_write_enable = GND;
SB1_q_a[1]_PORT_A_write_enable_reg = DFFE(SB1_q_a[1]_PORT_A_write_enable, SB1_q_a[1]_clock_0, , , );
SB1_q_a[1]_PORT_B_write_enable = TB1L62;
SB1_q_a[1]_PORT_B_write_enable_reg = DFFE(SB1_q_a[1]_PORT_B_write_enable, SB1_q_a[1]_clock_1, , , );
SB1_q_a[1]_clock_0 = CLK;
SB1_q_a[1]_clock_1 = A1L5;
SB1_q_a[1]_PORT_A_data_out = MEMORY(SB1_q_a[1]_PORT_A_data_in_reg, SB1_q_a[1]_PORT_B_data_in_reg, SB1_q_a[1]_PORT_A_address_reg, SB1_q_a[1]_PORT_B_address_reg, SB1_q_a[1]_PORT_A_write_enable_reg, SB1_q_a[1]_PORT_B_write_enable_reg, , , SB1_q_a[1]_clock_0, SB1_q_a[1]_clock_1, , , , );
SB1_q_a[1] = SB1_q_a[1]_PORT_A_data_out[0];

--SB1_q_b[1] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[1]
SB1_q_b[1]_PORT_A_data_in = VCC;
SB1_q_b[1]_PORT_A_data_in_reg = DFFE(SB1_q_b[1]_PORT_A_data_in, SB1_q_b[1]_clock_0, , , );
SB1_q_b[1]_PORT_B_data_in = TB1_ram_rom_data_reg[1];
SB1_q_b[1]_PORT_B_data_in_reg = DFFE(SB1_q_b[1]_PORT_B_data_in, SB1_q_b[1]_clock_1, , , );
SB1_q_b[1]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_b[1]_PORT_A_address_reg = DFFE(SB1_q_b[1]_PORT_A_address, SB1_q_b[1]_clock_0, , , );
SB1_q_b[1]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[1]_PORT_B_address_reg = DFFE(SB1_q_b[1]_PORT_B_address, SB1_q_b[1]_clock_1, , , );
SB1_q_b[1]_PORT_A_write_enable = GND;
SB1_q_b[1]_PORT_A_write_enable_reg = DFFE(SB1_q_b[1]_PORT_A_write_enable, SB1_q_b[1]_clock_0, , , );
SB1_q_b[1]_PORT_B_write_enable = TB1L62;
SB1_q_b[1]_PORT_B_write_enable_reg = DFFE(SB1_q_b[1]_PORT_B_write_enable, SB1_q_b[1]_clock_1, , , );
SB1_q_b[1]_clock_0 = CLK;
SB1_q_b[1]_clock_1 = A1L5;
SB1_q_b[1]_PORT_B_data_out = MEMORY(SB1_q_b[1]_PORT_A_data_in_reg, SB1_q_b[1]_PORT_B_data_in_reg, SB1_q_b[1]_PORT_A_address_reg, SB1_q_b[1]_PORT_B_address_reg, SB1_q_b[1]_PORT_A_write_enable_reg, SB1_q_b[1]_PORT_B_write_enable_reg, , , SB1_q_b[1]_clock_0, SB1_q_b[1]_clock_1, , , , );
SB1_q_b[1] = SB1_q_b[1]_PORT_B_data_out[0];


--SB1_q_a[0] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[0]_PORT_A_data_in = VCC;
SB1_q_a[0]_PORT_A_data_in_reg = DFFE(SB1_q_a[0]_PORT_A_data_in, SB1_q_a[0]_clock_0, , , );
SB1_q_a[0]_PORT_B_data_in = TB1_ram_rom_data_reg[0];
SB1_q_a[0]_PORT_B_data_in_reg = DFFE(SB1_q_a[0]_PORT_B_data_in, SB1_q_a[0]_clock_1, , , );
SB1_q_a[0]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_a[0]_PORT_A_address_reg = DFFE(SB1_q_a[0]_PORT_A_address, SB1_q_a[0]_clock_0, , , );
SB1_q_a[0]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_a[0]_PORT_B_address_reg = DFFE(SB1_q_a[0]_PORT_B_address, SB1_q_a[0]_clock_1, , , );
SB1_q_a[0]_PORT_A_write_enable = GND;
SB1_q_a[0]_PORT_A_write_enable_reg = DFFE(SB1_q_a[0]_PORT_A_write_enable, SB1_q_a[0]_clock_0, , , );
SB1_q_a[0]_PORT_B_write_enable = TB1L62;
SB1_q_a[0]_PORT_B_write_enable_reg = DFFE(SB1_q_a[0]_PORT_B_write_enable, SB1_q_a[0]_clock_1, , , );
SB1_q_a[0]_clock_0 = CLK;
SB1_q_a[0]_clock_1 = A1L5;
SB1_q_a[0]_PORT_A_data_out = MEMORY(SB1_q_a[0]_PORT_A_data_in_reg, SB1_q_a[0]_PORT_B_data_in_reg, SB1_q_a[0]_PORT_A_address_reg, SB1_q_a[0]_PORT_B_address_reg, SB1_q_a[0]_PORT_A_write_enable_reg, SB1_q_a[0]_PORT_B_write_enable_reg, , , SB1_q_a[0]_clock_0, SB1_q_a[0]_clock_1, , , , );
SB1_q_a[0] = SB1_q_a[0]_PORT_A_data_out[0];

--SB1_q_b[0] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[0]
SB1_q_b[0]_PORT_A_data_in = VCC;
SB1_q_b[0]_PORT_A_data_in_reg = DFFE(SB1_q_b[0]_PORT_A_data_in, SB1_q_b[0]_clock_0, , , );
SB1_q_b[0]_PORT_B_data_in = TB1_ram_rom_data_reg[0];
SB1_q_b[0]_PORT_B_data_in_reg = DFFE(SB1_q_b[0]_PORT_B_data_in, SB1_q_b[0]_clock_1, , , );
SB1_q_b[0]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_b[0]_PORT_A_address_reg = DFFE(SB1_q_b[0]_PORT_A_address, SB1_q_b[0]_clock_0, , , );
SB1_q_b[0]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[0]_PORT_B_address_reg = DFFE(SB1_q_b[0]_PORT_B_address, SB1_q_b[0]_clock_1, , , );
SB1_q_b[0]_PORT_A_write_enable = GND;
SB1_q_b[0]_PORT_A_write_enable_reg = DFFE(SB1_q_b[0]_PORT_A_write_enable, SB1_q_b[0]_clock_0, , , );
SB1_q_b[0]_PORT_B_write_enable = TB1L62;
SB1_q_b[0]_PORT_B_write_enable_reg = DFFE(SB1_q_b[0]_PORT_B_write_enable, SB1_q_b[0]_clock_1, , , );
SB1_q_b[0]_clock_0 = CLK;
SB1_q_b[0]_clock_1 = A1L5;
SB1_q_b[0]_PORT_B_data_out = MEMORY(SB1_q_b[0]_PORT_A_data_in_reg, SB1_q_b[0]_PORT_B_data_in_reg, SB1_q_b[0]_PORT_A_address_reg, SB1_q_b[0]_PORT_B_address_reg, SB1_q_b[0]_PORT_A_write_enable_reg, SB1_q_b[0]_PORT_B_write_enable_reg, , , SB1_q_b[0]_clock_0, SB1_q_b[0]_clock_1, , , , );
SB1_q_b[0] = SB1_q_b[0]_PORT_B_data_out[0];


--SB2_q_a[9] is SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[9]_PORT_A_data_in = VCC;
SB2_q_a[9]_PORT_A_data_in_reg = DFFE(SB2_q_a[9]_PORT_A_data_in, SB2_q_a[9]_clock_0, , , );
SB2_q_a[9]_PORT_B_data_in = TB2_ram_rom_data_reg[9];
SB2_q_a[9]_PORT_B_data_in_reg = DFFE(SB2_q_a[9]_PORT_B_data_in, SB2_q_a[9]_clock_1, , , );
SB2_q_a[9]_PORT_A_address = BUS(QB1_safe_q[9], QB1_safe_q[10], QB1_safe_q[11], QB1_safe_q[12], QB1_safe_q[13], QB1_safe_q[14], QB1_safe_q[15], QB1_safe_q[16], QB1_safe_q[17], QB1_safe_q[18]);
SB2_q_a[9]_PORT_A_address_reg = DFFE(SB2_q_a[9]_PORT_A_address, SB2_q_a[9]_clock_0, , , );
SB2_q_a[9]_PORT_B_address = BUS(UB2_safe_q[0], UB2_safe_q[1], UB2_safe_q[2], UB2_safe_q[3], UB2_safe_q[4], UB2_safe_q[5], UB2_safe_q[6], UB2_safe_q[7], UB2_safe_q[8], UB2_safe_q[9]);
SB2_q_a[9]_PORT_B_address_reg = DFFE(SB2_q_a[9]_PORT_B_address, SB2_q_a[9]_clock_1, , , );
SB2_q_a[9]_PORT_A_write_enable = GND;
SB2_q_a[9]_PORT_A_write_enable_reg = DFFE(SB2_q_a[9]_PORT_A_write_enable, SB2_q_a[9]_clock_0, , , );
SB2_q_a[9]_PORT_B_write_enable = TB2L62;
SB2_q_a[9]_PORT_B_write_enable_reg = DFFE(SB2_q_a[9]_PORT_B_write_enable, SB2_q_a[9]_clock_1, , , );
SB2_q_a[9]_clock_0 = CLK;
SB2_q_a[9]_clock_1 = A1L5;
SB2_q_a[9]_PORT_A_data_out = MEMORY(SB2_q_a[9]_PORT_A_data_in_reg, SB2_q_a[9]_PORT_B_data_in_reg, SB2_q_a[9]_PORT_A_address_reg, SB2_q_a[9]_PORT_B_address_reg, SB2_q_a[9]_PORT_A_write_enable_reg, SB2_q_a[9]_PORT_B_write_enable_reg, , , SB2_q_a[9]_clock_0, SB2_q_a[9]_clock_1, , , , );
SB2_q_a[9] = SB2_q_a[9]_PORT_A_data_out[0];

--SB2_q_b[9] is SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[9]
SB2_q_b[9]_PORT_A_data_in = VCC;
SB2_q_b[9]_PORT_A_data_in_reg = DFFE(SB2_q_b[9]_PORT_A_data_in, SB2_q_b[9]_clock_0, , , );
SB2_q_b[9]_PORT_B_data_in = TB2_ram_rom_data_reg[9];
SB2_q_b[9]_PORT_B_data_in_reg = DFFE(SB2_q_b[9]_PORT_B_data_in, SB2_q_b[9]_clock_1, , , );
SB2_q_b[9]_PORT_A_address = BUS(QB1_safe_q[9], QB1_safe_q[10], QB1_safe_q[11], QB1_safe_q[12], QB1_safe_q[13], QB1_safe_q[14], QB1_safe_q[15], QB1_safe_q[16], QB1_safe_q[17], QB1_safe_q[18]);
SB2_q_b[9]_PORT_A_address_reg = DFFE(SB2_q_b[9]_PORT_A_address, SB2_q_b[9]_clock_0, , , );
SB2_q_b[9]_PORT_B_address = BUS(UB2_safe_q[0], UB2_safe_q[1], UB2_safe_q[2], UB2_safe_q[3], UB2_safe_q[4], UB2_safe_q[5], UB2_safe_q[6], UB2_safe_q[7], UB2_safe_q[8], UB2_safe_q[9]);
SB2_q_b[9]_PORT_B_address_reg = DFFE(SB2_q_b[9]_PORT_B_address, SB2_q_b[9]_clock_1, , , );
SB2_q_b[9]_PORT_A_write_enable = GND;
SB2_q_b[9]_PORT_A_write_enable_reg = DFFE(SB2_q_b[9]_PORT_A_write_enable, SB2_q_b[9]_clock_0, , , );
SB2_q_b[9]_PORT_B_write_enable = TB2L62;
SB2_q_b[9]_PORT_B_write_enable_reg = DFFE(SB2_q_b[9]_PORT_B_write_enable, SB2_q_b[9]_clock_1, , , );
SB2_q_b[9]_clock_0 = CLK;
SB2_q_b[9]_clock_1 = A1L5;
SB2_q_b[9]_PORT_B_data_out = MEMORY(SB2_q_b[9]_PORT_A_data_in_reg, SB2_q_b[9]_PORT_B_data_in_reg, SB2_q_b[9]_PORT_A_address_reg, SB2_q_b[9]_PORT_B_address_reg, SB2_q_b[9]_PORT_A_write_enable_reg, SB2_q_b[9]_PORT_B_write_enable_reg, , , SB2_q_b[9]_clock_0, SB2_q_b[9]_clock_1, , , , );
SB2_q_b[9] = SB2_q_b[9]_PORT_B_data_out[0];


--SB2_q_a[8] is SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[8]
--RAM Block Operation Mode: True Dual-Port