dds_vhdl.map.eqn

这个是相当不错的EDA编程

SB1_q_b[6]_PORT_A_address_reg = DFFE(SB1_q_b[6]_PORT_A_address, SB1_q_b[6]_clock_0, , , );
SB1_q_b[6]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[6]_PORT_B_address_reg = DFFE(SB1_q_b[6]_PORT_B_address, SB1_q_b[6]_clock_1, , , );
SB1_q_b[6]_PORT_A_write_enable = GND;
SB1_q_b[6]_PORT_A_write_enable_reg = DFFE(SB1_q_b[6]_PORT_A_write_enable, SB1_q_b[6]_clock_0, , , );
SB1_q_b[6]_PORT_B_write_enable = TB1L62;
SB1_q_b[6]_PORT_B_write_enable_reg = DFFE(SB1_q_b[6]_PORT_B_write_enable, SB1_q_b[6]_clock_1, , , );
SB1_q_b[6]_clock_0 = CLK;
SB1_q_b[6]_clock_1 = A1L5;
SB1_q_b[6]_PORT_B_data_out = MEMORY(SB1_q_b[6]_PORT_A_data_in_reg, SB1_q_b[6]_PORT_B_data_in_reg, SB1_q_b[6]_PORT_A_address_reg, SB1_q_b[6]_PORT_B_address_reg, SB1_q_b[6]_PORT_A_write_enable_reg, SB1_q_b[6]_PORT_B_write_enable_reg, , , SB1_q_b[6]_clock_0, SB1_q_b[6]_clock_1, , , , );
SB1_q_b[6] = SB1_q_b[6]_PORT_B_data_out[0];


--SB1_q_a[5] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[5]_PORT_A_data_in = VCC;
SB1_q_a[5]_PORT_A_data_in_reg = DFFE(SB1_q_a[5]_PORT_A_data_in, SB1_q_a[5]_clock_0, , , );
SB1_q_a[5]_PORT_B_data_in = TB1_ram_rom_data_reg[5];
SB1_q_a[5]_PORT_B_data_in_reg = DFFE(SB1_q_a[5]_PORT_B_data_in, SB1_q_a[5]_clock_1, , , );
SB1_q_a[5]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_a[5]_PORT_A_address_reg = DFFE(SB1_q_a[5]_PORT_A_address, SB1_q_a[5]_clock_0, , , );
SB1_q_a[5]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_a[5]_PORT_B_address_reg = DFFE(SB1_q_a[5]_PORT_B_address, SB1_q_a[5]_clock_1, , , );
SB1_q_a[5]_PORT_A_write_enable = GND;
SB1_q_a[5]_PORT_A_write_enable_reg = DFFE(SB1_q_a[5]_PORT_A_write_enable, SB1_q_a[5]_clock_0, , , );
SB1_q_a[5]_PORT_B_write_enable = TB1L62;
SB1_q_a[5]_PORT_B_write_enable_reg = DFFE(SB1_q_a[5]_PORT_B_write_enable, SB1_q_a[5]_clock_1, , , );
SB1_q_a[5]_clock_0 = CLK;
SB1_q_a[5]_clock_1 = A1L5;
SB1_q_a[5]_PORT_A_data_out = MEMORY(SB1_q_a[5]_PORT_A_data_in_reg, SB1_q_a[5]_PORT_B_data_in_reg, SB1_q_a[5]_PORT_A_address_reg, SB1_q_a[5]_PORT_B_address_reg, SB1_q_a[5]_PORT_A_write_enable_reg, SB1_q_a[5]_PORT_B_write_enable_reg, , , SB1_q_a[5]_clock_0, SB1_q_a[5]_clock_1, , , , );
SB1_q_a[5] = SB1_q_a[5]_PORT_A_data_out[0];

--SB1_q_b[5] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[5]
SB1_q_b[5]_PORT_A_data_in = VCC;
SB1_q_b[5]_PORT_A_data_in_reg = DFFE(SB1_q_b[5]_PORT_A_data_in, SB1_q_b[5]_clock_0, , , );
SB1_q_b[5]_PORT_B_data_in = TB1_ram_rom_data_reg[5];
SB1_q_b[5]_PORT_B_data_in_reg = DFFE(SB1_q_b[5]_PORT_B_data_in, SB1_q_b[5]_clock_1, , , );
SB1_q_b[5]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_b[5]_PORT_A_address_reg = DFFE(SB1_q_b[5]_PORT_A_address, SB1_q_b[5]_clock_0, , , );
SB1_q_b[5]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[5]_PORT_B_address_reg = DFFE(SB1_q_b[5]_PORT_B_address, SB1_q_b[5]_clock_1, , , );
SB1_q_b[5]_PORT_A_write_enable = GND;
SB1_q_b[5]_PORT_A_write_enable_reg = DFFE(SB1_q_b[5]_PORT_A_write_enable, SB1_q_b[5]_clock_0, , , );
SB1_q_b[5]_PORT_B_write_enable = TB1L62;
SB1_q_b[5]_PORT_B_write_enable_reg = DFFE(SB1_q_b[5]_PORT_B_write_enable, SB1_q_b[5]_clock_1, , , );
SB1_q_b[5]_clock_0 = CLK;
SB1_q_b[5]_clock_1 = A1L5;
SB1_q_b[5]_PORT_B_data_out = MEMORY(SB1_q_b[5]_PORT_A_data_in_reg, SB1_q_b[5]_PORT_B_data_in_reg, SB1_q_b[5]_PORT_A_address_reg, SB1_q_b[5]_PORT_B_address_reg, SB1_q_b[5]_PORT_A_write_enable_reg, SB1_q_b[5]_PORT_B_write_enable_reg, , , SB1_q_b[5]_clock_0, SB1_q_b[5]_clock_1, , , , );
SB1_q_b[5] = SB1_q_b[5]_PORT_B_data_out[0];


--SB1_q_a[4] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[4]_PORT_A_data_in = VCC;
SB1_q_a[4]_PORT_A_data_in_reg = DFFE(SB1_q_a[4]_PORT_A_data_in, SB1_q_a[4]_clock_0, , , );
SB1_q_a[4]_PORT_B_data_in = TB1_ram_rom_data_reg[4];
SB1_q_a[4]_PORT_B_data_in_reg = DFFE(SB1_q_a[4]_PORT_B_data_in, SB1_q_a[4]_clock_1, , , );
SB1_q_a[4]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_a[4]_PORT_A_address_reg = DFFE(SB1_q_a[4]_PORT_A_address, SB1_q_a[4]_clock_0, , , );
SB1_q_a[4]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_a[4]_PORT_B_address_reg = DFFE(SB1_q_a[4]_PORT_B_address, SB1_q_a[4]_clock_1, , , );
SB1_q_a[4]_PORT_A_write_enable = GND;
SB1_q_a[4]_PORT_A_write_enable_reg = DFFE(SB1_q_a[4]_PORT_A_write_enable, SB1_q_a[4]_clock_0, , , );
SB1_q_a[4]_PORT_B_write_enable = TB1L62;
SB1_q_a[4]_PORT_B_write_enable_reg = DFFE(SB1_q_a[4]_PORT_B_write_enable, SB1_q_a[4]_clock_1, , , );
SB1_q_a[4]_clock_0 = CLK;
SB1_q_a[4]_clock_1 = A1L5;
SB1_q_a[4]_PORT_A_data_out = MEMORY(SB1_q_a[4]_PORT_A_data_in_reg, SB1_q_a[4]_PORT_B_data_in_reg, SB1_q_a[4]_PORT_A_address_reg, SB1_q_a[4]_PORT_B_address_reg, SB1_q_a[4]_PORT_A_write_enable_reg, SB1_q_a[4]_PORT_B_write_enable_reg, , , SB1_q_a[4]_clock_0, SB1_q_a[4]_clock_1, , , , );
SB1_q_a[4] = SB1_q_a[4]_PORT_A_data_out[0];

--SB1_q_b[4] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[4]
SB1_q_b[4]_PORT_A_data_in = VCC;
SB1_q_b[4]_PORT_A_data_in_reg = DFFE(SB1_q_b[4]_PORT_A_data_in, SB1_q_b[4]_clock_0, , , );
SB1_q_b[4]_PORT_B_data_in = TB1_ram_rom_data_reg[4];
SB1_q_b[4]_PORT_B_data_in_reg = DFFE(SB1_q_b[4]_PORT_B_data_in, SB1_q_b[4]_clock_1, , , );
SB1_q_b[4]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_b[4]_PORT_A_address_reg = DFFE(SB1_q_b[4]_PORT_A_address, SB1_q_b[4]_clock_0, , , );
SB1_q_b[4]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[4]_PORT_B_address_reg = DFFE(SB1_q_b[4]_PORT_B_address, SB1_q_b[4]_clock_1, , , );
SB1_q_b[4]_PORT_A_write_enable = GND;
SB1_q_b[4]_PORT_A_write_enable_reg = DFFE(SB1_q_b[4]_PORT_A_write_enable, SB1_q_b[4]_clock_0, , , );
SB1_q_b[4]_PORT_B_write_enable = TB1L62;
SB1_q_b[4]_PORT_B_write_enable_reg = DFFE(SB1_q_b[4]_PORT_B_write_enable, SB1_q_b[4]_clock_1, , , );
SB1_q_b[4]_clock_0 = CLK;
SB1_q_b[4]_clock_1 = A1L5;
SB1_q_b[4]_PORT_B_data_out = MEMORY(SB1_q_b[4]_PORT_A_data_in_reg, SB1_q_b[4]_PORT_B_data_in_reg, SB1_q_b[4]_PORT_A_address_reg, SB1_q_b[4]_PORT_B_address_reg, SB1_q_b[4]_PORT_A_write_enable_reg, SB1_q_b[4]_PORT_B_write_enable_reg, , , SB1_q_b[4]_clock_0, SB1_q_b[4]_clock_1, , , , );
SB1_q_b[4] = SB1_q_b[4]_PORT_B_data_out[0];


--SB1_q_a[3] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[3]_PORT_A_data_in = VCC;
SB1_q_a[3]_PORT_A_data_in_reg = DFFE(SB1_q_a[3]_PORT_A_data_in, SB1_q_a[3]_clock_0, , , );
SB1_q_a[3]_PORT_B_data_in = TB1_ram_rom_data_reg[3];
SB1_q_a[3]_PORT_B_data_in_reg = DFFE(SB1_q_a[3]_PORT_B_data_in, SB1_q_a[3]_clock_1, , , );
SB1_q_a[3]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_a[3]_PORT_A_address_reg = DFFE(SB1_q_a[3]_PORT_A_address, SB1_q_a[3]_clock_0, , , );
SB1_q_a[3]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_a[3]_PORT_B_address_reg = DFFE(SB1_q_a[3]_PORT_B_address, SB1_q_a[3]_clock_1, , , );
SB1_q_a[3]_PORT_A_write_enable = GND;
SB1_q_a[3]_PORT_A_write_enable_reg = DFFE(SB1_q_a[3]_PORT_A_write_enable, SB1_q_a[3]_clock_0, , , );
SB1_q_a[3]_PORT_B_write_enable = TB1L62;
SB1_q_a[3]_PORT_B_write_enable_reg = DFFE(SB1_q_a[3]_PORT_B_write_enable, SB1_q_a[3]_clock_1, , , );
SB1_q_a[3]_clock_0 = CLK;
SB1_q_a[3]_clock_1 = A1L5;
SB1_q_a[3]_PORT_A_data_out = MEMORY(SB1_q_a[3]_PORT_A_data_in_reg, SB1_q_a[3]_PORT_B_data_in_reg, SB1_q_a[3]_PORT_A_address_reg, SB1_q_a[3]_PORT_B_address_reg, SB1_q_a[3]_PORT_A_write_enable_reg, SB1_q_a[3]_PORT_B_write_enable_reg, , , SB1_q_a[3]_clock_0, SB1_q_a[3]_clock_1, , , , );
SB1_q_a[3] = SB1_q_a[3]_PORT_A_data_out[0];

--SB1_q_b[3] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[3]
SB1_q_b[3]_PORT_A_data_in = VCC;
SB1_q_b[3]_PORT_A_data_in_reg = DFFE(SB1_q_b[3]_PORT_A_data_in, SB1_q_b[3]_clock_0, , , );
SB1_q_b[3]_PORT_B_data_in = TB1_ram_rom_data_reg[3];
SB1_q_b[3]_PORT_B_data_in_reg = DFFE(SB1_q_b[3]_PORT_B_data_in, SB1_q_b[3]_clock_1, , , );
SB1_q_b[3]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_b[3]_PORT_A_address_reg = DFFE(SB1_q_b[3]_PORT_A_address, SB1_q_b[3]_clock_0, , , );
SB1_q_b[3]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_b[3]_PORT_B_address_reg = DFFE(SB1_q_b[3]_PORT_B_address, SB1_q_b[3]_clock_1, , , );
SB1_q_b[3]_PORT_A_write_enable = GND;
SB1_q_b[3]_PORT_A_write_enable_reg = DFFE(SB1_q_b[3]_PORT_A_write_enable, SB1_q_b[3]_clock_0, , , );
SB1_q_b[3]_PORT_B_write_enable = TB1L62;
SB1_q_b[3]_PORT_B_write_enable_reg = DFFE(SB1_q_b[3]_PORT_B_write_enable, SB1_q_b[3]_clock_1, , , );
SB1_q_b[3]_clock_0 = CLK;
SB1_q_b[3]_clock_1 = A1L5;
SB1_q_b[3]_PORT_B_data_out = MEMORY(SB1_q_b[3]_PORT_A_data_in_reg, SB1_q_b[3]_PORT_B_data_in_reg, SB1_q_b[3]_PORT_A_address_reg, SB1_q_b[3]_PORT_B_address_reg, SB1_q_b[3]_PORT_A_write_enable_reg, SB1_q_b[3]_PORT_B_write_enable_reg, , , SB1_q_b[3]_clock_0, SB1_q_b[3]_clock_1, , , , );
SB1_q_b[3] = SB1_q_b[3]_PORT_B_data_out[0];


--SB1_q_a[2] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[2]_PORT_A_data_in = VCC;
SB1_q_a[2]_PORT_A_data_in_reg = DFFE(SB1_q_a[2]_PORT_A_data_in, SB1_q_a[2]_clock_0, , , );
SB1_q_a[2]_PORT_B_data_in = TB1_ram_rom_data_reg[2];
SB1_q_a[2]_PORT_B_data_in_reg = DFFE(SB1_q_a[2]_PORT_B_data_in, SB1_q_a[2]_clock_1, , , );
SB1_q_a[2]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
SB1_q_a[2]_PORT_A_address_reg = DFFE(SB1_q_a[2]_PORT_A_address, SB1_q_a[2]_clock_0, , , );
SB1_q_a[2]_PORT_B_address = BUS(UB1_safe_q[0], UB1_safe_q[1], UB1_safe_q[2], UB1_safe_q[3], UB1_safe_q[4], UB1_safe_q[5], UB1_safe_q[6], UB1_safe_q[7], UB1_safe_q[8], UB1_safe_q[9]);
SB1_q_a[2]_PORT_B_address_reg = DFFE(SB1_q_a[2]_PORT_B_address, SB1_q_a[2]_clock_1, , , );
SB1_q_a[2]_PORT_A_write_enable = GND;
SB1_q_a[2]_PORT_A_write_enable_reg = DFFE(SB1_q_a[2]_PORT_A_write_enable, SB1_q_a[2]_clock_0, , , );