dds_vhdl.hier_info

这个是相当不错的EDA编程

address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[8] => ram_block3a8.PORTAADDR8
address_a[8] => ram_block3a9.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9
address_a[9] => ram_block3a6.PORTAADDR9
address_a[9] => ram_block3a7.PORTAADDR9
address_a[9] => ram_block3a8.PORTAADDR9
address_a[9] => ram_block3a9.PORTAADDR9
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[0] => ram_block3a8.PORTBADDR
address_b[0] => ram_block3a9.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[1] => ram_block3a8.PORTBADDR1
address_b[1] => ram_block3a9.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[2] => ram_block3a8.PORTBADDR2
address_b[2] => ram_block3a9.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[3] => ram_block3a8.PORTBADDR3
address_b[3] => ram_block3a9.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[4] => ram_block3a8.PORTBADDR4
address_b[4] => ram_block3a9.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[5] => ram_block3a8.PORTBADDR5
address_b[5] => ram_block3a9.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[6] => ram_block3a8.PORTBADDR6
address_b[6] => ram_block3a9.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
address_b[7] => ram_block3a8.PORTBADDR7
address_b[7] => ram_block3a9.PORTBADDR7
address_b[8] => ram_block3a0.PORTBADDR8
address_b[8] => ram_block3a1.PORTBADDR8
address_b[8] => ram_block3a2.PORTBADDR8
address_b[8] => ram_block3a3.PORTBADDR8
address_b[8] => ram_block3a4.PORTBADDR8
address_b[8] => ram_block3a5.PORTBADDR8
address_b[8] => ram_block3a6.PORTBADDR8
address_b[8] => ram_block3a7.PORTBADDR8
address_b[8] => ram_block3a8.PORTBADDR8
address_b[8] => ram_block3a9.PORTBADDR8
address_b[9] => ram_block3a0.PORTBADDR9
address_b[9] => ram_block3a1.PORTBADDR9
address_b[9] => ram_block3a2.PORTBADDR9
address_b[9] => ram_block3a3.PORTBADDR9
address_b[9] => ram_block3a4.PORTBADDR9
address_b[9] => ram_block3a5.PORTBADDR9
address_b[9] => ram_block3a6.PORTBADDR9
address_b[9] => ram_block3a7.PORTBADDR9
address_b[9] => ram_block3a8.PORTBADDR9
address_b[9] => ram_block3a9.PORTBADDR9
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock0 => ram_block3a8.CLK0
clock0 => ram_block3a9.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
clock1 => ram_block3a8.CLK1
clock1 => ram_block3a9.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
data_b[8] => ram_block3a8.PORTBDATAIN
data_b[9] => ram_block3a9.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_a[8] <= ram_block3a8.PORTADATAOUT
q_a[9] <= ram_block3a9.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
q_b[8] <= ram_block3a8.PORTBDATAOUT
q_b[9] <= ram_block3a9.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE
wren_b => ram_block3a8.PORTBRE
wren_b => ram_block3a9.PORTBRE


|DDS_VHDL|SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
address[8] <= ram_rom_addr_reg[8].DB_MAX_OUTPUT_PORT_TYPE
address[9] <= ram_rom_addr_reg[9].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= ram_rom_incr_addr~1.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_write[8] <= ram_rom_data_reg[8].DB_MAX_OUTPUT_PORT_TYPE
data_write[9] <= ram_rom_data_reg[9].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~19.DATAB
data_read[1] => ram_rom_data_reg~18.DATAB
data_read[2] => ram_rom_data_reg~17.DATAB
data_read[3] => ram_rom_data_reg~16.DATAB
data_read[4] => ram_rom_data_reg~15.DATAB
data_read[5] => ram_rom_data_reg~14.DATAB
data_read[6] => ram_rom_data_reg~13.DATAB
data_read[7] => ram_rom_data_reg~12.DATAB
data_read[8] => ram_rom_data_reg~11.DATAB
data_read[9] => ram_rom_data_reg~10.DATAB
raw_tck => ram_rom_addr_reg[8].CLK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[9].CLK
raw_tck => ram_rom_data_reg[8].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[6].CLK
raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ram_rom_incr_write_addr_reg.CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => is_in_use_reg.CLK
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK
raw_tck => ram_rom_addr_reg[9].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~0.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN0
usr1 => name_gen~0.IN0
jtag_state_cdr => name_gen~1.IN1
jtag_state_sdr => sdr.IN0
jtag_state_sdr => name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => e1dr.IN1
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN1
ena => name_gen~0.IN1
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[8].ACLR
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => ir_loaded_address_reg[3].ACLR
ir_in[0] => ir_loaded_address_reg[2].ACLR
ir_in[0] => ir_loaded_address_reg[1].ACLR
ir_in[0] => ir_loaded_address_reg[0].ACLR
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[9].ACLR
ir_in[1] => process1~0.IN1
ir_in[1] => process1~2.IN0
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~0.IN0
ir_in[2] => ram_rom_incr_addr~1.IN1
ir_in[3] => process0~0.IN1
ir_in[3] => process1~3.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process5~0.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|DDS_VHDL|SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux~0.IN134
ROM_DATA[0] => Mux~1.IN134
ROM_DATA[0] => Mux~2.IN134
ROM_DATA[0] => Mux~3.IN134
ROM_DATA[1] => Mux~0.IN133
ROM_DATA[1] => Mux~1.IN133
ROM_DATA[1] => Mux~2.IN133
ROM_DATA[1] => Mux~3.IN133
ROM_DATA[2] => Mux~0.IN132
ROM_DATA[2] => Mux~1.IN132
ROM_DATA[2] => Mux~2.IN132
ROM_DATA[2] => Mux~3.IN132
ROM_DATA[3] => Mux~0.IN131
ROM_DATA[3] => Mux~1.IN131
ROM_DATA[3] => Mux~2.IN131
ROM_DATA[3] => Mux~3.IN131
ROM_DATA[4] => Mux~0.IN130
ROM_DATA[4] => Mux~1.IN130
ROM_DATA[4] => Mux~2.IN130