dds_vhdl.hier_info

这个是相当不错的EDA编程

|DDS_VHDL
CLK => sin_rom:u6.inclock
CLK => reg10b:u5.Load
CLK => sin_rom:u3.inclock
CLK => reg32b:u2.Load
CLK => clK20M.DATAIN
FWORD[0] => ~NO_FANOUT~
FWORD[1] => ~NO_FANOUT~
FWORD[2] => ~NO_FANOUT~
FWORD[3] => ~NO_FANOUT~
FWORD[4] => ~NO_FANOUT~
FWORD[5] => ~NO_FANOUT~
FWORD[6] => ~NO_FANOUT~
FWORD[7] => ~NO_FANOUT~
PWORD[0] => adder10b:u4.A[2]
PWORD[1] => adder10b:u4.A[3]
PWORD[2] => adder10b:u4.A[4]
PWORD[3] => adder10b:u4.A[5]
PWORD[4] => adder10b:u4.A[6]
PWORD[5] => adder10b:u4.A[7]
PWORD[6] => adder10b:u4.A[8]
PWORD[7] => adder10b:u4.A[9]
FOUT[0] <= sin_rom:u3.q[0]
FOUT[1] <= sin_rom:u3.q[1]
FOUT[2] <= sin_rom:u3.q[2]
FOUT[3] <= sin_rom:u3.q[3]
FOUT[4] <= sin_rom:u3.q[4]
FOUT[5] <= sin_rom:u3.q[5]
FOUT[6] <= sin_rom:u3.q[6]
FOUT[7] <= sin_rom:u3.q[7]
FOUT[8] <= sin_rom:u3.q[8]
FOUT[9] <= sin_rom:u3.q[9]
POUT[0] <= sin_rom:u6.q[0]
POUT[1] <= sin_rom:u6.q[1]
POUT[2] <= sin_rom:u6.q[2]
POUT[3] <= sin_rom:u6.q[3]
POUT[4] <= sin_rom:u6.q[4]
POUT[5] <= sin_rom:u6.q[5]
POUT[6] <= sin_rom:u6.q[6]
POUT[7] <= sin_rom:u6.q[7]
POUT[8] <= sin_rom:u6.q[8]
POUT[9] <= sin_rom:u6.q[9]
clK20M <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|DDS_VHDL|ADDER32B:u1
A[0] => add~0.IN32
A[1] => add~0.IN31
A[2] => add~0.IN30
A[3] => add~0.IN29
A[4] => add~0.IN28
A[5] => add~0.IN27
A[6] => add~0.IN26
A[7] => add~0.IN25
A[8] => add~0.IN24
A[9] => add~0.IN23
A[10] => add~0.IN22
A[11] => add~0.IN21
A[12] => add~0.IN20
A[13] => add~0.IN19
A[14] => add~0.IN18
A[15] => add~0.IN17
A[16] => add~0.IN16
A[17] => add~0.IN15
A[18] => add~0.IN14
A[19] => add~0.IN13
A[20] => add~0.IN12
A[21] => add~0.IN11
A[22] => add~0.IN10
A[23] => add~0.IN9
A[24] => add~0.IN8
A[25] => add~0.IN7
A[26] => add~0.IN6
A[27] => add~0.IN5
A[28] => add~0.IN4
A[29] => add~0.IN3
A[30] => add~0.IN2
A[31] => add~0.IN1
B[0] => add~0.IN64
B[1] => add~0.IN63
B[2] => add~0.IN62
B[3] => add~0.IN61
B[4] => add~0.IN60
B[5] => add~0.IN59
B[6] => add~0.IN58
B[7] => add~0.IN57
B[8] => add~0.IN56
B[9] => add~0.IN55
B[10] => add~0.IN54
B[11] => add~0.IN53
B[12] => add~0.IN52
B[13] => add~0.IN51
B[14] => add~0.IN50
B[15] => add~0.IN49
B[16] => add~0.IN48
B[17] => add~0.IN47
B[18] => add~0.IN46
B[19] => add~0.IN45
B[20] => add~0.IN44
B[21] => add~0.IN43
B[22] => add~0.IN42
B[23] => add~0.IN41
B[24] => add~0.IN40
B[25] => add~0.IN39
B[26] => add~0.IN38
B[27] => add~0.IN37
B[28] => add~0.IN36
B[29] => add~0.IN35
B[30] => add~0.IN34
B[31] => add~0.IN33
S[0] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[7] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[8] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[9] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[10] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[11] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[12] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[13] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[14] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[15] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[16] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[17] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[18] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[19] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[20] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[21] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[22] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[23] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[24] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[25] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[26] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[27] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[28] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[29] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[30] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
S[31] <= add~0.DB_MAX_OUTPUT_PORT_TYPE


|DDS_VHDL|REG32B:u2
Load => DOUT[30]~reg0.CLK
Load => DOUT[29]~reg0.CLK
Load => DOUT[28]~reg0.CLK
Load => DOUT[27]~reg0.CLK
Load => DOUT[26]~reg0.CLK
Load => DOUT[25]~reg0.CLK
Load => DOUT[24]~reg0.CLK
Load => DOUT[23]~reg0.CLK
Load => DOUT[22]~reg0.CLK
Load => DOUT[21]~reg0.CLK
Load => DOUT[20]~reg0.CLK
Load => DOUT[19]~reg0.CLK
Load => DOUT[18]~reg0.CLK
Load => DOUT[17]~reg0.CLK
Load => DOUT[16]~reg0.CLK
Load => DOUT[15]~reg0.CLK
Load => DOUT[14]~reg0.CLK
Load => DOUT[13]~reg0.CLK
Load => DOUT[12]~reg0.CLK
Load => DOUT[11]~reg0.CLK
Load => DOUT[10]~reg0.CLK
Load => DOUT[9]~reg0.CLK
Load => DOUT[8]~reg0.CLK
Load => DOUT[7]~reg0.CLK
Load => DOUT[6]~reg0.CLK
Load => DOUT[5]~reg0.CLK
Load => DOUT[4]~reg0.CLK
Load => DOUT[3]~reg0.CLK
Load => DOUT[2]~reg0.CLK
Load => DOUT[1]~reg0.CLK
Load => DOUT[0]~reg0.CLK
Load => DOUT[31]~reg0.CLK
DIN[0] => DOUT[0]~reg0.DATAIN
DIN[1] => DOUT[1]~reg0.DATAIN
DIN[2] => DOUT[2]~reg0.DATAIN
DIN[3] => DOUT[3]~reg0.DATAIN
DIN[4] => DOUT[4]~reg0.DATAIN
DIN[5] => DOUT[5]~reg0.DATAIN
DIN[6] => DOUT[6]~reg0.DATAIN
DIN[7] => DOUT[7]~reg0.DATAIN
DIN[8] => DOUT[8]~reg0.DATAIN
DIN[9] => DOUT[9]~reg0.DATAIN
DIN[10] => DOUT[10]~reg0.DATAIN
DIN[11] => DOUT[11]~reg0.DATAIN
DIN[12] => DOUT[12]~reg0.DATAIN
DIN[13] => DOUT[13]~reg0.DATAIN
DIN[14] => DOUT[14]~reg0.DATAIN
DIN[15] => DOUT[15]~reg0.DATAIN
DIN[16] => DOUT[16]~reg0.DATAIN
DIN[17] => DOUT[17]~reg0.DATAIN
DIN[18] => DOUT[18]~reg0.DATAIN
DIN[19] => DOUT[19]~reg0.DATAIN
DIN[20] => DOUT[20]~reg0.DATAIN
DIN[21] => DOUT[21]~reg0.DATAIN
DIN[22] => DOUT[22]~reg0.DATAIN
DIN[23] => DOUT[23]~reg0.DATAIN
DIN[24] => DOUT[24]~reg0.DATAIN
DIN[25] => DOUT[25]~reg0.DATAIN
DIN[26] => DOUT[26]~reg0.DATAIN
DIN[27] => DOUT[27]~reg0.DATAIN
DIN[28] => DOUT[28]~reg0.DATAIN
DIN[29] => DOUT[29]~reg0.DATAIN
DIN[30] => DOUT[30]~reg0.DATAIN
DIN[31] => DOUT[31]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= DOUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[8] <= DOUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[9] <= DOUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[10] <= DOUT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[11] <= DOUT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[12] <= DOUT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[13] <= DOUT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[14] <= DOUT[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[15] <= DOUT[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[16] <= DOUT[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[17] <= DOUT[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[18] <= DOUT[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[19] <= DOUT[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[20] <= DOUT[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[21] <= DOUT[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[22] <= DOUT[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[23] <= DOUT[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[24] <= DOUT[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[25] <= DOUT[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[26] <= DOUT[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[27] <= DOUT[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[28] <= DOUT[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[29] <= DOUT[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[30] <= DOUT[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[31] <= DOUT[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS_VHDL|SIN_ROM:u3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|DDS_VHDL|SIN_ROM:u3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_gmu:auto_generated.address_a[0]
address_a[1] => altsyncram_gmu:auto_generated.address_a[1]
address_a[2] => altsyncram_gmu:auto_generated.address_a[2]
address_a[3] => altsyncram_gmu:auto_generated.address_a[3]
address_a[4] => altsyncram_gmu:auto_generated.address_a[4]
address_a[5] => altsyncram_gmu:auto_generated.address_a[5]
address_a[6] => altsyncram_gmu:auto_generated.address_a[6]
address_a[7] => altsyncram_gmu:auto_generated.address_a[7]
address_a[8] => altsyncram_gmu:auto_generated.address_a[8]
address_a[9] => altsyncram_gmu:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_gmu:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_gmu:auto_generated.q_a[0]
q_a[1] <= altsyncram_gmu:auto_generated.q_a[1]
q_a[2] <= altsyncram_gmu:auto_generated.q_a[2]
q_a[3] <= altsyncram_gmu:auto_generated.q_a[3]
q_a[4] <= altsyncram_gmu:auto_generated.q_a[4]
q_a[5] <= altsyncram_gmu:auto_generated.q_a[5]
q_a[6] <= altsyncram_gmu:auto_generated.q_a[6]
q_a[7] <= altsyncram_gmu:auto_generated.q_a[7]
q_a[8] <= altsyncram_gmu:auto_generated.q_a[8]
q_a[9] <= altsyncram_gmu:auto_generated.q_a[9]
q_b[0] <= <UNC>


|DDS_VHDL|SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated
address_a[0] => altsyncram_8kc2:altsyncram1.address_a[0]
address_a[1] => altsyncram_8kc2:altsyncram1.address_a[1]
address_a[2] => altsyncram_8kc2:altsyncram1.address_a[2]
address_a[3] => altsyncram_8kc2:altsyncram1.address_a[3]
address_a[4] => altsyncram_8kc2:altsyncram1.address_a[4]
address_a[5] => altsyncram_8kc2:altsyncram1.address_a[5]
address_a[6] => altsyncram_8kc2:altsyncram1.address_a[6]
address_a[7] => altsyncram_8kc2:altsyncram1.address_a[7]
address_a[8] => altsyncram_8kc2:altsyncram1.address_a[8]
address_a[9] => altsyncram_8kc2:altsyncram1.address_a[9]
clock0 => altsyncram_8kc2:altsyncram1.clock0
q_a[0] <= altsyncram_8kc2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_8kc2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_8kc2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_8kc2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_8kc2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_8kc2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_8kc2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_8kc2:altsyncram1.q_a[7]
q_a[8] <= altsyncram_8kc2:altsyncram1.q_a[8]
q_a[9] <= altsyncram_8kc2:altsyncram1.q_a[9]


|DDS_VHDL|SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3