dds_vhdl.fit.qmsg

这个是相当不错的EDA编程

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "5 " "Info: Fitter routing operations ending: elapsed time = 5 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] " "Info: Port clear -- assigned as a global for destination node SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] " "Info: Port clear -- assigned as a global for destination node SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] " "Info: Port clear -- assigned as a global for destination node SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] " "Info: Port clear -- assigned as a global for destination node SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] " "Info: Port clear -- assigned as a global for destination node SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] " "Info: Port clear -- assigned as a global for destination node SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Node sld_signaltap:auto_signaltap_0\|reset_all uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[2\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[2\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[2\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd" 1154 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[107\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[107\] -- routed using non-global resources" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[107] } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[107\]" } } } } { "f:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[107] } "NODE_NAME" } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 412 -1 0 } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 10 08:45:24 2005 " "Info: Processing ended: Sat Sep 10 08:45:24 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Info: Elapsed time: 00:00:40" {  } {  } 0}  } {  } 0}