dds_vhdl.fit.qmsg

这个是相当不错的EDA编程

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "17 unused 3.30 16 1 0 " "Info: Number of I/O pins in group: 17 (unused VREF, 3.30 VCCIO, 16 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 6 22 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  22 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 12 16 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  16 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 6 22 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  22 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 6 22 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  22 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 13 15 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 13 total pin(s) used --  15 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 22 6 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 22 total pin(s) used --  6 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "6 " "Info: Fitter placement preparation operations ending: elapsed time = 6 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.021 ns register register " "Info: Estimated most critical path is register to register delay of 4.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[3\] 1 REG LAB_X10_Y9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[3\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[3] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.442 ns) 1.396 ns sld_hub:sld_hub_inst\|HUB_TDO~818 2 COMB LAB_X9_Y7 1 " "Info: 2: + IC(0.954 ns) + CELL(0.442 ns) = 1.396 ns; Loc. = LAB_X9_Y7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~818'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.396 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[3] sld_hub:sld_hub_inst|HUB_TDO~818 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.590 ns) 2.677 ns sld_hub:sld_hub_inst\|HUB_TDO~819 3 COMB LAB_X10_Y10 1 " "Info: 3: + IC(0.691 ns) + CELL(0.590 ns) = 2.677 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~819'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.281 ns" { sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.287 ns) + CELL(0.292 ns) 3.256 ns sld_hub:sld_hub_inst\|HUB_TDO~820 4 COMB LAB_X10_Y10 1 " "Info: 4: + IC(0.287 ns) + CELL(0.292 ns) = 3.256 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~820'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.579 ns" { sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.287 ns) + CELL(0.478 ns) 4.021 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 5 REG LAB_X10_Y10 0 " "Info: 5: + IC(0.287 ns) + CELL(0.478 ns) = 4.021 ns; Loc. = LAB_X10_Y10; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.765 ns" { sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns 44.81 % " "Info: Total cell delay = 1.802 ns ( 44.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.219 ns 55.19 % " "Info: Total interconnect delay = 2.219 ns ( 55.19 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.021 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[3] sld_hub:sld_hub_inst|HUB_TDO~818 sld_hub:sld_hub_inst|HUB_TDO~819 sld_hub:sld_hub_inst|HUB_TDO~820 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "10 " "Info: Estimated interconnect usage is 10% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "6 " "Info: Fitter placement operations ending: elapsed time = 6 seconds" {  } {  } 0}