dds_vhdl.fit.qmsg

这个是相当不错的EDA编程

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|reset_all Global clock " "Info: Automatically promoted some destinations of signal sld_signaltap:auto_signaltap_0\|reset_all to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29 " "Info: Destination sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29 may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_acquisition_buffer.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0}  } { { "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 412 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 to use Global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal Global clock " "Info: Automatically promoted signal sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal to use Global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|HUB_TDO~813 " "Info: Destination sld_hub:sld_hub_inst\|HUB_TDO~813 may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 756 -1 0 } }  } 0}  } { { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|HUB_TDO~816 " "Info: Destination sld_hub:sld_hub_inst\|HUB_TDO~816 may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 756 -1 0 } }  } 0}  } { { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] may be non-global or may not use global clock" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0}  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}