dds_vhdl.fit.qmsg

这个是相当不错的EDA编程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 10 08:44:43 2005 " "Info: Processing started: Sat Sep 10 08:44:43 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off DDS_VHDL -c dds_vhdl " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off DDS_VHDL -c dds_vhdl" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dds_vhdl EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design dds_vhdl" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "21 42 " "Info: No exact pin location assignment(s) for 21 pins of 42 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clK20M " "Info: Pin clK20M not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 10 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clK20M" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { clK20M } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { clK20M } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_reserved_tdo } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_reserved_tms } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_reserved_tck } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_reserved_tdi } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[0\] " "Info: Pin PWORD\[0\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[0\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[0] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[1\] " "Info: Pin PWORD\[1\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[1\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[1] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[2\] " "Info: Pin PWORD\[2\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[2\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[2] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[3\] " "Info: Pin PWORD\[3\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[3\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[3] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[4\] " "Info: Pin PWORD\[4\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[4\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[4] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[5\] " "Info: Pin PWORD\[5\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[5\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[5] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[6\] " "Info: Pin PWORD\[6\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[6\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[6] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PWORD\[7\] " "Info: Pin PWORD\[7\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PWORD\[7\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[7] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { PWORD[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[0\] " "Info: Pin FWORD\[0\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[0\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[0] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[1\] " "Info: Pin FWORD\[1\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[1\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[1] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[2\] " "Info: Pin FWORD\[2\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[2\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[2] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[3\] " "Info: Pin FWORD\[3\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[3\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[3] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[4\] " "Info: Pin FWORD\[4\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[4\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[4] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[5\] " "Info: Pin FWORD\[5\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[5\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[5] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[6\] " "Info: Pin FWORD\[6\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[6\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[6] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[7\] " "Info: Pin FWORD\[7\] not assigned to an exact location on the device" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 6 -1 0 } } { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[7\]" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { FWORD[7] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { FWORD[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLK Global clock in PIN 16 " "Info: Automatically promoted some destinations of signal CLK to use Global clock in PIN 16" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clK20M " "Info: Destination clK20M may be non-global or may not use global clock" {  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 10 -1 0 } }  } 0}  } { { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal altera_internal_jtag~TCKUTAP to use Global clock" {  } { { "f:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "f:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { Floorplan "F:/A_matiral/DDS_1k/dds_vhdl.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}