dds_vhdl.tan.qmsg

这个是相当不错的EDA编程

{ "Info" "ITDB_FULL_TPD_RESULT" "CLK clK20M 5.000 ns Longest " "Info: Longest tpd from source pin CLK to destination pin clK20M is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 439 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 439; CLK Node = 'CLK'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(2.108 ns) 5.000 ns clK20M 2 PIN PIN_143 0 " "Info: 2: + IC(1.423 ns) + CELL(2.108 ns) = 5.000 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'clK20M'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "3.531 ns" { CLK clK20M } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.577 ns 71.54 % " "Info: Total cell delay = 3.577 ns ( 71.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.423 ns 28.46 % " "Info: Total interconnect delay = 1.423 ns ( 28.46 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "5.000 ns" { CLK clK20M } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[15\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 3.370 ns register " "Info: th for register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[15\] (data pin = altera_internal_jtag~TMSUTAP, clock pin = altera_internal_jtag~TCKUTAP) is 3.370 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.882 ns + Longest register " "Info: + Longest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 522 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 522; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.171 ns) + CELL(0.711 ns) 4.882 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[15\] 2 REG LC_X8_Y9_N7 3 " "Info: 2: + IC(4.171 ns) + CELL(0.711 ns) = 4.882 ns; Loc. = LC_X8_Y9_N7; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[15\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.56 % " "Info: Total cell delay = 0.711 ns ( 14.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.171 ns 85.44 % " "Info: Total interconnect delay = 4.171 ns ( 85.44 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.527 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.527 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y6_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.309 ns) 1.527 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[15\] 2 REG LC_X8_Y9_N7 3 " "Info: 2: + IC(1.218 ns) + CELL(0.309 ns) = 1.527 ns; Loc. = LC_X8_Y9_N7; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[15\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.527 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 20.24 % " "Info: Total cell delay = 0.309 ns ( 20.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.218 ns 79.76 % " "Info: Total interconnect delay = 1.218 ns ( 79.76 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.527 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] } "NODE_NAME" } } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.527 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK FOUT\[3\] SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a6~porta_address_reg9 11.049 ns memory " "Info: Minimum tco from clock CLK to destination pin FOUT\[3\] through memory SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a6~porta_address_reg9 is 11.049 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.770 ns + Shortest memory " "Info: + Shortest clock path from clock CLK to source memory is 2.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 439 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 439; CLK Node = 'CLK'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.722 ns) 2.770 ns SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a6~porta_address_reg9 2 MEM M4K_X13_Y13 4 " "Info: 2: + IC(0.579 ns) + CELL(0.722 ns) = 2.770 ns; Loc. = M4K_X13_Y13; Fanout = 4; MEM Node = 'SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a6~porta_address_reg9'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.301 ns" { CLK SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 235 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.10 % " "Info: Total cell delay = 2.191 ns ( 79.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.90 % " "Info: Total interconnect delay = 0.579 ns ( 20.90 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 235 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.629 ns + Shortest memory pin " "Info: + Shortest memory to pin delay is 7.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a6~porta_address_reg9 1 MEM M4K_X13_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y13; Fanout = 4; MEM Node = 'SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a6~porta_address_reg9'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 235 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|q_a\[3\] 2 MEM M4K_X13_Y13 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y13; Fanout = 2; MEM Node = 'SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|q_a\[3\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.308 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[3] } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(2.108 ns) 7.629 ns FOUT\[3\] 3 PIN PIN_126 0 " "Info: 3: + IC(1.213 ns) + CELL(2.108 ns) = 7.629 ns; Loc. = PIN_126; Fanout = 0; PIN Node = 'FOUT\[3\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "3.321 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[3] FOUT[3] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns 84.10 % " "Info: Total cell delay = 6.416 ns ( 84.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.213 ns 15.90 % " "Info: Total interconnect delay = 1.213 ns ( 15.90 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "7.629 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[3] FOUT[3] } "NODE_NAME" } } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "7.629 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[3] FOUT[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Shortest " "Info: Shortest tpd from source pin altera_internal_jtag~TDO to destination pin altera_reserved_tdo is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0}