dds_vhdl.tan.qmsg

这个是相当不错的EDA编程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a4~porta_address_reg0 register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[18\] 134.01 MHz 7.462 ns Internal " "Info: Clock CLK has Internal fmax of 134.01 MHz between source memory SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a4~porta_address_reg0 and destination register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[18\] (period= 7.462 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.726 ns + Longest memory register " "Info: + Longest memory to register delay is 6.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a4~porta_address_reg0 1 MEM M4K_X13_Y10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y10; Fanout = 2; MEM Node = 'SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a4~porta_address_reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 171 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|q_a\[0\] 2 MEM M4K_X13_Y10 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y10; Fanout = 2; MEM Node = 'SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|q_a\[0\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.308 ns" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[0] } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.303 ns) + CELL(0.115 ns) 6.726 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[18\] 3 REG LC_X20_Y5_N3 3 " "Info: 3: + IC(2.303 ns) + CELL(0.115 ns) = 6.726 ns; Loc. = LC_X20_Y5_N3; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[18\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.418 ns" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[0] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.423 ns 65.76 % " "Info: Total cell delay = 4.423 ns ( 65.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.303 ns 34.24 % " "Info: Total interconnect delay = 2.303 ns ( 34.24 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "6.726 ns" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[0] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.049 ns - Smallest " "Info: - Smallest clock skew is -0.049 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.721 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 439 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 439; CLK Node = 'CLK'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[18\] 2 REG LC_X20_Y5_N3 3 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X20_Y5_N3; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[18\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.252 ns" { CLK sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.721 ns" { CLK sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.770 ns - Longest memory " "Info: - Longest clock path from clock CLK to source memory is 2.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 439 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 439; CLK Node = 'CLK'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.722 ns) 2.770 ns SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a4~porta_address_reg0 2 MEM M4K_X13_Y10 2 " "Info: 2: + IC(0.579 ns) + CELL(0.722 ns) = 2.770 ns; Loc. = M4K_X13_Y10; Fanout = 2; MEM Node = 'SIN_ROM:u6\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a4~porta_address_reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.301 ns" { CLK SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 171 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.10 % " "Info: Total cell delay = 2.191 ns ( 79.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.90 % " "Info: Total interconnect delay = 0.579 ns ( 20.90 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 } "NODE_NAME" } } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.721 ns" { CLK sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 171 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "6.726 ns" { SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[0] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.721 ns" { CLK sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] register sld_hub:sld_hub_inst\|HUB_TDO~reg0 110.5 MHz 9.05 ns Internal " "Info: Clock altera_internal_jtag~TCKUTAP has Internal fmax of 110.5 MHz between source register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] and destination register sld_hub:sld_hub_inst\|HUB_TDO~reg0 (period= 9.05 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.264 ns + Longest register register " "Info: + Longest register to register delay is 4.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 1 REG LC_X8_Y12_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y12_N0; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.217 ns) + CELL(0.442 ns) 1.659 ns sld_hub:sld_hub_inst\|HUB_TDO~812 2 COMB LC_X12_Y12_N4 1 " "Info: 2: + IC(1.217 ns) + CELL(0.442 ns) = 1.659 ns; Loc. = LC_X12_Y12_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~812'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.659 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|HUB_TDO~812 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.114 ns) 3.343 ns sld_hub:sld_hub_inst\|HUB_TDO~813 3 COMB LC_X10_Y10_N9 1 " "Info: 3: + IC(1.570 ns) + CELL(0.114 ns) = 3.343 ns; Loc. = LC_X10_Y10_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~813'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.684 ns" { sld_hub:sld_hub_inst|HUB_TDO~812 sld_hub:sld_hub_inst|HUB_TDO~813 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.478 ns) 4.264 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 4 REG LC_X10_Y10_N4 0 " "Info: 4: + IC(0.443 ns) + CELL(0.478 ns) = 4.264 ns; Loc. = LC_X10_Y10_N4; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.921 ns" { sld_hub:sld_hub_inst|HUB_TDO~813 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.034 ns 24.25 % " "Info: Total cell delay = 1.034 ns ( 24.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.230 ns 75.75 % " "Info: Total interconnect delay = 3.230 ns ( 75.75 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.264 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|HUB_TDO~812 sld_hub:sld_hub_inst|HUB_TDO~813 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.882 ns + Shortest register " "Info: + Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 522 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 522; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.171 ns) + CELL(0.711 ns) 4.882 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X10_Y10_N4 0 " "Info: 2: + IC(4.171 ns) + CELL(0.711 ns) = 4.882 ns; Loc. = LC_X10_Y10_N4; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.56 % " "Info: Total cell delay = 0.711 ns ( 14.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.171 ns 85.44 % " "Info: Total interconnect delay = 4.171 ns ( 85.44 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.882 ns - Longest register " "Info: - Longest clock path from clock altera_internal_jtag~TCKUTAP to source register is 4.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 522 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 522; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.171 ns) + CELL(0.711 ns) 4.882 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 2 REG LC_X8_Y12_N0 5 " "Info: 2: + IC(4.171 ns) + CELL(0.711 ns) = 4.882 ns; Loc. = LC_X8_Y12_N0; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } } { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.56 % " "Info: Total cell delay = 0.711 ns ( 14.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.171 ns 85.44 % " "Info: Total interconnect delay = 4.171 ns ( 85.44 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "f:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.264 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|HUB_TDO~812 sld_hub:sld_hub_inst|HUB_TDO~813 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.882 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "REG10B:u5\|DOUT\[7\] PWORD\[1\] CLK 7.291 ns register " "Info: tsu for register REG10B:u5\|DOUT\[7\] (data pin = PWORD\[1\], clock pin = CLK) is 7.291 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.013 ns + Longest pin register " "Info: + Longest pin to register delay is 10.013 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns PWORD\[1\] 1 PIN PIN_54 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_54; Fanout = 4; PIN Node = 'PWORD\[1\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { PWORD[1] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.423 ns) 8.840 ns REG10B:u5\|DOUT\[3\]~COUT0 2 COMB LC_X15_Y9_N1 2 " "Info: 2: + IC(6.942 ns) + CELL(0.423 ns) = 8.840 ns; Loc. = LC_X15_Y9_N1; Fanout = 2; COMB Node = 'REG10B:u5\|DOUT\[3\]~COUT0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "7.365 ns" { PWORD[1] REG10B:u5|DOUT[3]~COUT0 } "NODE_NAME" } } } { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 8.918 ns REG10B:u5\|DOUT\[4\]~COUT0 3 COMB LC_X15_Y9_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 8.918 ns; Loc. = LC_X15_Y9_N2; Fanout = 2; COMB Node = 'REG10B:u5\|DOUT\[4\]~COUT0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.078 ns" { REG10B:u5|DOUT[3]~COUT0 REG10B:u5|DOUT[4]~COUT0 } "NODE_NAME" } } } { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 8.996 ns REG10B:u5\|DOUT\[5\]~COUT0 4 COMB LC_X15_Y9_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 8.996 ns; Loc. = LC_X15_Y9_N3; Fanout = 2; COMB Node = 'REG10B:u5\|DOUT\[5\]~COUT0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.078 ns" { REG10B:u5|DOUT[4]~COUT0 REG10B:u5|DOUT[5]~COUT0 } "NODE_NAME" } } } { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 9.174 ns REG10B:u5\|DOUT\[6\]~COUT 5 COMB LC_X15_Y9_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 9.174 ns; Loc. = LC_X15_Y9_N4; Fanout = 3; COMB Node = 'REG10B:u5\|DOUT\[6\]~COUT'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.178 ns" { REG10B:u5|DOUT[5]~COUT0 REG10B:u5|DOUT[6]~COUT } "NODE_NAME" } } } { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 10.013 ns REG10B:u5\|DOUT\[7\] 6 REG LC_X15_Y9_N5 3 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 10.013 ns; Loc. = LC_X15_Y9_N5; Fanout = 3; REG Node = 'REG10B:u5\|DOUT\[7\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "0.839 ns" { REG10B:u5|DOUT[6]~COUT REG10B:u5|DOUT[7] } "NODE_NAME" } } } { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.071 ns 30.67 % " "Info: Total cell delay = 3.071 ns ( 30.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.942 ns 69.33 % " "Info: Total interconnect delay = 6.942 ns ( 69.33 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "10.013 ns" { PWORD[1] REG10B:u5|DOUT[3]~COUT0 REG10B:u5|DOUT[4]~COUT0 REG10B:u5|DOUT[5]~COUT0 REG10B:u5|DOUT[6]~COUT REG10B:u5|DOUT[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.759 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 439 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 439; CLK Node = 'CLK'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.711 ns) 2.759 ns REG10B:u5\|DOUT\[7\] 2 REG LC_X15_Y9_N5 3 " "Info: 2: + IC(0.579 ns) + CELL(0.711 ns) = 2.759 ns; Loc. = LC_X15_Y9_N5; Fanout = 3; REG Node = 'REG10B:u5\|DOUT\[7\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.290 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } } { "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" "" "" { Text "F:/eda/experiment/Experiments/Chapter13_C/EP1C3_13_10_PHAS/reg10b.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.01 % " "Info: Total cell delay = 2.180 ns ( 79.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.99 % " "Info: Total interconnect delay = 0.579 ns ( 20.99 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.759 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "10.013 ns" { PWORD[1] REG10B:u5|DOUT[3]~COUT0 REG10B:u5|DOUT[4]~COUT0 REG10B:u5|DOUT[5]~COUT0 REG10B:u5|DOUT[6]~COUT REG10B:u5|DOUT[7] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.759 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[9\] SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a9~porta_address_reg0 13.481 ns memory " "Info: tco from clock CLK to destination pin FOUT\[9\] through memory SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a9~porta_address_reg0 is 13.481 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.770 ns + Longest memory " "Info: + Longest clock path from clock CLK to source memory is 2.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 439 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 439; CLK Node = 'CLK'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.722 ns) 2.770 ns SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a9~porta_address_reg0 2 MEM M4K_X13_Y12 4 " "Info: 2: + IC(0.579 ns) + CELL(0.722 ns) = 2.770 ns; Loc. = M4K_X13_Y12; Fanout = 4; MEM Node = 'SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a9~porta_address_reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "1.301 ns" { CLK SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 331 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.10 % " "Info: Total cell delay = 2.191 ns ( 79.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.90 % " "Info: Total interconnect delay = 0.579 ns ( 20.90 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 331 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.061 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a9~porta_address_reg0 1 MEM M4K_X13_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y12; Fanout = 4; MEM Node = 'SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|ram_block3a9~porta_address_reg0'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 331 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|q_a\[9\] 2 MEM M4K_X13_Y12 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y12; Fanout = 2; MEM Node = 'SIN_ROM:u3\|altsyncram:altsyncram_component\|altsyncram_gmu:auto_generated\|altsyncram_8kc2:altsyncram1\|q_a\[9\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "4.308 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9] } "NODE_NAME" } } } { "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" "" "" { Text "F:/EP1C3_13_10_PHAS/db/altsyncram_8kc2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.629 ns) + CELL(2.124 ns) 10.061 ns FOUT\[9\] 3 PIN PIN_77 0 " "Info: 3: + IC(3.629 ns) + CELL(2.124 ns) = 10.061 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'FOUT\[9\]'" {  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "5.753 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9] FOUT[9] } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/dds_vhdl.vhd" "" "" { Text "F:/A_matiral/DDS_1k/dds_vhdl.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.432 ns 63.93 % " "Info: Total cell delay = 6.432 ns ( 63.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.629 ns 36.07 % " "Info: Total interconnect delay = 3.629 ns ( 36.07 % )" {  } {  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "10.061 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9] FOUT[9] } "NODE_NAME" } } }  } 0}  } { { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "2.770 ns" { CLK SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } } { "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" "" "" { Report "F:/A_matiral/DDS_1k/db/dds_vhdl_cmp.qrpt" Compiler "dds_vhdl" "UNKNOWN" "V1" "F:/A_matiral/DDS_1k/db/DDS_VHDL.quartus_db" { Floorplan "" "" "10.061 ns" { SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg0 SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9] FOUT[9] } "NODE_NAME" } } }  } 0}