dds_all.fit.qmsg

这个是相当不错的EDA编程

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 Global clock " "Info: Automatically promoted signal \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" to use Global clock" {  } { { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a8 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a8\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a7 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a7\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a6 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a6\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a5 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a5\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a4 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a4\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a3 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a3\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a1 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a1\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a0 clk0 GND " "Warning: WYSIWYG primitive \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a0\" has port clk0 that is stuck at GND" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } } { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } } { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "WYSIWYG primitive \"%1!s!\" has port %2!s! that is stuck at %3!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}