dds_all.fit.qmsg

这个是相当不错的EDA编程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 20 10:13:34 2007 " "Info: Processing started: Mon Aug 20 10:13:34 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DDS_ALL -c DDS_ALL " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS_ALL -c DDS_ALL" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DDS_ALL EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"DDS_ALL\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "tt:inst1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"tt:inst1\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "tt:inst1\|altpll:altpll_component\|_clk0 3 1 0 0 " "Info: Implementing clock multiplication of 3, clock division of 1, and phase shift of 0 degrees (0 ps) for tt:inst1\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "tt.vhd" "" { Text "E:/EDA/DDS_all/tt.vhd" 93 -1 0 } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 48 -56 216 208 "inst1" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "tt:inst1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"tt:inst1\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "tt:inst1\|altpll:altpll_component\|_clk0" } { 0 "tt:inst1\|altpll:altpll_component\|_clk0" } } } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 48 -56 216 208 "inst1" "" } } } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|CLR_SIGNAL\" to use Global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~980 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~980\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~981 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~981\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~983 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~983\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~984 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~984\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"SIN_ROM:inst6\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 Global clock " "Info: Automatically promoted signal \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" to use Global clock" {  } { { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}