dds_all.hier_info

这个是相当不错的EDA编程

DIN[31] => DOUT[31]~reg0.DATAIN
DOUT[0] <= DOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= DOUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[8] <= DOUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[9] <= DOUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[10] <= DOUT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[11] <= DOUT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[12] <= DOUT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[13] <= DOUT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[14] <= DOUT[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[15] <= DOUT[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[16] <= DOUT[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[17] <= DOUT[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[18] <= DOUT[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[19] <= DOUT[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[20] <= DOUT[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[21] <= DOUT[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[22] <= DOUT[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[23] <= DOUT[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[24] <= DOUT[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[25] <= DOUT[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[26] <= DOUT[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[27] <= DOUT[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[28] <= DOUT[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[29] <= DOUT[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[30] <= DOUT[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DOUT[31] <= DOUT[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS_ALL|ADDER32B:inst2
A[0] => Add0.IN32
A[1] => Add0.IN31
A[2] => Add0.IN30
A[3] => Add0.IN29
A[4] => Add0.IN28
A[5] => Add0.IN27
A[6] => Add0.IN26
A[7] => Add0.IN25
A[8] => Add0.IN24
A[9] => Add0.IN23
A[10] => Add0.IN22
A[11] => Add0.IN21
A[12] => Add0.IN20
A[13] => Add0.IN19
A[14] => Add0.IN18
A[15] => Add0.IN17
A[16] => Add0.IN16
A[17] => Add0.IN15
A[18] => Add0.IN14
A[19] => Add0.IN13
A[20] => Add0.IN12
A[21] => Add0.IN11
A[22] => Add0.IN10
A[23] => Add0.IN9
A[24] => Add0.IN8
A[25] => Add0.IN7
A[26] => Add0.IN6
A[27] => Add0.IN5
A[28] => Add0.IN4
A[29] => Add0.IN3
A[30] => Add0.IN2
A[31] => Add0.IN1
B[0] => Add0.IN64
B[1] => Add0.IN63
B[2] => Add0.IN62
B[3] => Add0.IN61
B[4] => Add0.IN60
B[5] => Add0.IN59
B[6] => Add0.IN58
B[7] => Add0.IN57
B[8] => Add0.IN56
B[9] => Add0.IN55
B[10] => Add0.IN54
B[11] => Add0.IN53
B[12] => Add0.IN52
B[13] => Add0.IN51
B[14] => Add0.IN50
B[15] => Add0.IN49
B[16] => Add0.IN48
B[17] => Add0.IN47
B[18] => Add0.IN46
B[19] => Add0.IN45
B[20] => Add0.IN44
B[21] => Add0.IN43
B[22] => Add0.IN42
B[23] => Add0.IN41
B[24] => Add0.IN40
B[25] => Add0.IN39
B[26] => Add0.IN38
B[27] => Add0.IN37
B[28] => Add0.IN36
B[29] => Add0.IN35
B[30] => Add0.IN34
B[31] => Add0.IN33
S[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
S[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|DDS_ALL|word:inst14
clk => ~NO_FANOUT~
Set[0] => ~NO_FANOUT~
Set[1] => ~NO_FANOUT~
Set[2] => ~NO_FANOUT~
Set[3] => ~NO_FANOUT~
cnt[0] => ~NO_FANOUT~
cnt[1] => ~NO_FANOUT~
Fword[0] => ~NO_FANOUT~
Fword[1] => ~NO_FANOUT~
Fword[2] => ~NO_FANOUT~
Fword[3] => ~NO_FANOUT~
Fword[4] => ~NO_FANOUT~
Fword[5] => ~NO_FANOUT~
Fword[6] => ~NO_FANOUT~
Fword[7] => ~NO_FANOUT~
Pword[0] => ~NO_FANOUT~
Pword[1] => ~NO_FANOUT~
Pword[2] => ~NO_FANOUT~
Pword[3] => ~NO_FANOUT~
Pword[4] => ~NO_FANOUT~
Pword[5] => ~NO_FANOUT~
Pword[6] => ~NO_FANOUT~
Pword[7] => ~NO_FANOUT~
P[0] <= <GND>
P[1] <= <GND>
P[2] <= <GND>
P[3] <= <GND>
P[4] <= <GND>
P[5] <= <GND>
P[6] <= <GND>
P[7] <= <GND>
P[8] <= <GND>
P[9] <= <GND>
F[0] <= <GND>
F[1] <= <GND>
F[2] <= <GND>
F[3] <= <GND>
F[4] <= <GND>
F[5] <= <GND>
F[6] <= <GND>
F[7] <= <GND>
F[8] <= <GND>
F[9] <= <GND>
F[10] <= <GND>
F[11] <= <GND>
F[12] <= <GND>
F[13] <= <GND>
F[14] <= <GND>
F[15] <= <GND>
F[16] <= <GND>
F[17] <= <GND>
F[18] <= <GND>
F[19] <= <GND>
F[20] <= <GND>
F[21] <= <GND>
F[22] <= <GND>
F[23] <= <GND>
F[24] <= <GND>
F[25] <= <GND>
F[26] <= <GND>
F[27] <= <GND>
F[28] <= <GND>
F[29] <= <GND>
F[30] <= <GND>
F[31] <= <GND>


|DDS_ALL|MODE1:inst11
clk => ~NO_FANOUT~
Pset => process1~0.IN0
Pset => process1~1.IN0
Setkey[0] => Equal0.IN7
Setkey[1] => Equal0.IN6
Setkey[2] => Equal0.IN5
Setkey[3] => Equal0.IN4


|DDS_ALL|SIN_ROM:inst6
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|DDS_ALL|SIN_ROM:inst6|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_sq71:auto_generated.address_a[0]
address_a[1] => altsyncram_sq71:auto_generated.address_a[1]
address_a[2] => altsyncram_sq71:auto_generated.address_a[2]
address_a[3] => altsyncram_sq71:auto_generated.address_a[3]
address_a[4] => altsyncram_sq71:auto_generated.address_a[4]
address_a[5] => altsyncram_sq71:auto_generated.address_a[5]
address_a[6] => altsyncram_sq71:auto_generated.address_a[6]
address_a[7] => altsyncram_sq71:auto_generated.address_a[7]
address_a[8] => altsyncram_sq71:auto_generated.address_a[8]
address_a[9] => altsyncram_sq71:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_sq71:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_sq71:auto_generated.q_a[0]
q_a[1] <= altsyncram_sq71:auto_generated.q_a[1]
q_a[2] <= altsyncram_sq71:auto_generated.q_a[2]
q_a[3] <= altsyncram_sq71:auto_generated.q_a[3]
q_a[4] <= altsyncram_sq71:auto_generated.q_a[4]
q_a[5] <= altsyncram_sq71:auto_generated.q_a[5]
q_a[6] <= altsyncram_sq71:auto_generated.q_a[6]
q_a[7] <= altsyncram_sq71:auto_generated.q_a[7]
q_a[8] <= altsyncram_sq71:auto_generated.q_a[8]
q_a[9] <= altsyncram_sq71:auto_generated.q_a[9]
q_b[0] <= <GND>


|DDS_ALL|SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated
address_a[0] => altsyncram_kol2:altsyncram1.address_a[0]
address_a[1] => altsyncram_kol2:altsyncram1.address_a[1]
address_a[2] => altsyncram_kol2:altsyncram1.address_a[2]
address_a[3] => altsyncram_kol2:altsyncram1.address_a[3]
address_a[4] => altsyncram_kol2:altsyncram1.address_a[4]
address_a[5] => altsyncram_kol2:altsyncram1.address_a[5]
address_a[6] => altsyncram_kol2:altsyncram1.address_a[6]
address_a[7] => altsyncram_kol2:altsyncram1.address_a[7]
address_a[8] => altsyncram_kol2:altsyncram1.address_a[8]
address_a[9] => altsyncram_kol2:altsyncram1.address_a[9]
clock0 => altsyncram_kol2:altsyncram1.clock0
q_a[0] <= altsyncram_kol2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_kol2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_kol2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_kol2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_kol2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_kol2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_kol2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_kol2:altsyncram1.q_a[7]
q_a[8] <= altsyncram_kol2:altsyncram1.q_a[8]
q_a[9] <= altsyncram_kol2:altsyncram1.q_a[9]


|DDS_ALL|SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[8] => ram_block3a8.PORTAADDR8
address_a[8] => ram_block3a9.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9