dds_all.map.qmsg

这个是相当不错的EDA编程

{ "Info" "ISGN_ELABORATION_HEADER" "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/quartus/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "d:/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "d:/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\", which is child of megafunction instantiation \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } } { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 0000000000 " "Info: Parameter \"CVALUE\" = \"0000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1919905024 " "Info: Parameter \"NODE_NAME\" = \"1919905024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 1024 " "Info: Parameter \"NUMWORDS\" = \"1024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 4 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 10 " "Info: Parameter \"WIDTH_WORD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 10 " "Info: Parameter \"WIDTHAD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tt tt:inst1 " "Info: Elaborating entity \"tt\" for hierarchy \"tt:inst1\"" {  } { { "DDS_ALL.bdf" "inst1" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 48 -56 216 208 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll tt:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"tt:inst1\|altpll:altpll_component\"" {  } { { "tt.vhd" "altpll_component" { Text "E:/EDA/DDS_all/tt.vhd" 93 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "tt:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"tt:inst1\|altpll:altpll_component\"" {  } { { "tt.vhd" "" { Text "E:/EDA/DDS_all/tt.vhd" 93 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG10B REG10B:inst4 " "Info: Elaborating entity \"REG10B\" for hierarchy \"REG10B:inst4\"" {  } { { "DDS_ALL.bdf" "inst4" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 128 504 664 224 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER10B ADDER10B:inst " "Info: Elaborating entity \"ADDER10B\" for hierarchy \"ADDER10B:inst\"" {  } { { "DDS_ALL.bdf" "inst" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 144 336 456 240 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG32B REG32B:inst3 " "Info: Elaborating entity \"REG32B\" for hierarchy \"REG32B:inst3\"" {  } { { "DDS_ALL.bdf" "inst3" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 520 688 400 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER32B ADDER32B:inst2 " "Info: Elaborating entity \"ADDER32B\" for hierarchy \"ADDER32B:inst2\"" {  } { { "DDS_ALL.bdf" "inst2" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 320 320 448 416 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "word word:inst14 " "Info: Elaborating entity \"word\" for hierarchy \"word:inst14\"" {  } { { "DDS_ALL.bdf" "inst14" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 320 72 216 448 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "temp_F word.vhd(19) " "Warning (10036): Verilog HDL or VHDL warning at word.vhd(19): object \"temp_F\" assigned a value but never read" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "temp_P word.vhd(20) " "Warning (10036): Verilog HDL or VHDL warning at word.vhd(20): object \"temp_P\" assigned a value but never read" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_set word.vhd(26) " "Warning (10492): VHDL Process Statement warning at word.vhd(26): signal \"temp_set\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(31) " "Warning (10492): VHDL Process Statement warning at word.vhd(31): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(36) " "Warning (10492): VHDL Process Statement warning at word.vhd(36): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(45) " "Warning (10492): VHDL Process Statement warning at word.vhd(45): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 45 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(50) " "Warning (10492): VHDL Process Statement warning at word.vhd(50): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 50 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(59) " "Warning (10492): VHDL Process Statement warning at word.vhd(59): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 59 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(64) " "Warning (10492): VHDL Process Statement warning at word.vhd(64): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 64 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(73) " "Warning (10492): VHDL Process Statement warning at word.vhd(73): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 73 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Pword word.vhd(78) " "Warning (10492): VHDL Process Statement warning at word.vhd(78): signal \"Pword\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 78 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "P\[9\] word.vhd(11) " "Warning (10034): Output port \"P\[9\]\" at word.vhd(11) has no driver" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 11 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}