dds_all.map.qmsg

这个是相当不错的EDA编程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 20 10:13:18 2007 " "Info: Processing started: Mon Aug 20 10:13:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS_ALL -c DDS_ALL " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS_ALL -c DDS_ALL" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER10B.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER10B.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "ADDER10B.VHD" "" { Text "E:/EDA/DDS_all/ADDER10B.VHD" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "ADDER10B.VHD" "" { Text "E:/EDA/DDS_all/ADDER10B.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER32B.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER32B.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER32B-behav " "Info: Found design unit 1: ADDER32B-behav" {  } { { "ADDER32B.VHD" "" { Text "E:/EDA/DDS_all/ADDER32B.VHD" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER32B " "Info: Found entity 1: ADDER32B" {  } { { "ADDER32B.VHD" "" { Text "E:/EDA/DDS_all/ADDER32B.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS_ALL.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDS_ALL.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDS_ALL " "Info: Found entity 1: DDS_ALL" {  } { { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds_vhdl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dds_vhdl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS_VHDL-one " "Info: Found design unit 1: DDS_VHDL-one" {  } { { "dds_vhdl.vhd" "" { Text "E:/EDA/DDS_all/dds_vhdl.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS_VHDL " "Info: Found entity 1: DDS_VHDL" {  } { { "dds_vhdl.vhd" "" { Text "E:/EDA/DDS_all/dds_vhdl.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG10B.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG10B.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "REG10B.VHD" "" { Text "E:/EDA/DDS_all/REG10B.VHD" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "REG10B.VHD" "" { Text "E:/EDA/DDS_all/REG10B.VHD" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG32B.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG32B.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG32B-behav " "Info: Found design unit 1: REG32B-behav" {  } { { "REG32B.VHD" "" { Text "E:/EDA/DDS_all/REG32B.VHD" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG32B " "Info: Found entity 1: REG32B" {  } { { "REG32B.VHD" "" { Text "E:/EDA/DDS_all/REG32B.VHD" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIN_ROM.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file SIN_ROM.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN_ROM " "Info: Found entity 1: SIN_ROM" {  } { { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tt-SYN " "Info: Found design unit 1: tt-SYN" {  } { { "tt.vhd" "" { Text "E:/EDA/DDS_all/tt.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tt " "Info: Found entity 1: tt" {  } { { "tt.vhd" "" { Text "E:/EDA/DDS_all/tt.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MODE1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file MODE1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MODE1-behav " "Info: Found design unit 1: MODE1-behav" {  } { { "MODE1.vhd" "" { Text "E:/EDA/DDS_all/MODE1.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 MODE1 " "Info: Found entity 1: MODE1" {  } { { "MODE1.vhd" "" { Text "E:/EDA/DDS_all/MODE1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "word.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file word.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 word-behav " "Info: Found design unit 1: word-behav" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 word " "Info: Found entity 1: word" {  } { { "word.vhd" "" { Text "E:/EDA/DDS_all/word.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS_ALL " "Info: Elaborating entity \"DDS_ALL\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "inclock SIN_ROM inst6 " "Warning: Port \"inclock\" of type SIN_ROM and instance \"inst6\" is missing source signal" {  } { { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 304 832 984 400 "inst6" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SIN_ROM SIN_ROM:inst5 " "Info: Elaborating entity \"SIN_ROM\" for hierarchy \"SIN_ROM:inst5\"" {  } { { "DDS_ALL.bdf" "inst5" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 128 728 880 224 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram SIN_ROM:inst5\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"SIN_ROM:inst5\|altsyncram:altsyncram_component\"" {  } { { "SIN_ROM.VHD" "altsyncram_component" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "SIN_ROM:inst5\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"SIN_ROM:inst5\|altsyncram:altsyncram_component\"" {  } { { "SIN_ROM.VHD" "" { Text "E:/EDA/DDS_all/SIN_ROM.VHD" 86 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sq71.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sq71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sq71 " "Info: Found entity 1: altsyncram_sq71" {  } { { "db/altsyncram_sq71.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sq71 SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated " "Info: Elaborating entity \"altsyncram_sq71\" for hierarchy \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/quartus/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_kol2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kol2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_kol2 " "Info: Found entity 1: altsyncram_kol2" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_kol2 SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1 " "Info: Elaborating entity \"altsyncram_kol2\" for hierarchy \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\"" {  } { { "db/altsyncram_sq71.tdf" "altsyncram1" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "F:/EP1C3_13_10_PHAS/DATA/LUT10X10.MIF " "Critical Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File F:/EP1C3_13_10_PHAS/DATA/LUT10X10.MIF -- setting all initial values to 0" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 48 2 0 } }  } 1 0 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_sq71.tdf" "mgl_prim2" { Text "E:/EDA/DDS_all/db/altsyncram_sq71.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}