dds_all.tan.qmsg

这个是相当不错的EDA编程

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 memory SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1 memory SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1 4.928 ns " "Info: Minimum slack time is 4.928 ns for clock \"tt:inst1\|altpll:altpll_component\|_clk0\" between source memory \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1\" and destination memory \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Shortest memory memory " "Info: + Shortest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1 1 MEM M4K_X13_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1 2 MEM M4K_X13_Y10 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y10; Fanout = 0; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.609 ns - Smallest memory memory " "Info: - Smallest memory to memory requirement is -0.609 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.833 ns " "Info: + Latch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination tt:inst1\|altpll:altpll_component\|_clk0 16.666 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"tt:inst1\|altpll:altpll_component\|_clk0\" is 16.666 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source tt:inst1\|altpll:altpll_component\|_clk0 16.666 ns -1.833 ns  50 " "Info: Clock period of Source clock \"tt:inst1\|altpll:altpll_component\|_clk0\" is 16.666 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Smallest " "Info: + Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 destination 2.315 ns + Longest memory " "Info: + Longest clock path from clock \"tt:inst1\|altpll:altpll_component\|_clk0\" to destination memory is 2.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tt:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 53; CLK Node = 'tt:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.708 ns) 2.315 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1 2 MEM M4K_X13_Y10 0 " "Info: 2: + IC(1.607 ns) + CELL(0.708 ns) = 2.315 ns; Loc. = M4K_X13_Y10; Fanout = 0; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 30.58 % ) " "Info: Total cell delay = 0.708 ns ( 30.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.42 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 source 2.329 ns - Shortest memory " "Info: - Shortest clock path from clock \"tt:inst1\|altpll:altpll_component\|_clk0\" to source memory is 2.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tt:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 53; CLK Node = 'tt:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.722 ns) 2.329 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1 2 MEM M4K_X13_Y10 1 " "Info: 2: + IC(1.607 ns) + CELL(0.722 ns) = 2.329 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 31.00 % ) " "Info: Total cell delay = 0.722 ns ( 31.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.00 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP -0.451 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is -0.451 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.784 ns + Longest pin register " "Info: + Longest pin to register delay is 4.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y6_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.767 ns) + CELL(0.590 ns) 2.357 ns sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21 2 COMB LC_X17_Y6_N4 3 " "Info: 2: + IC(1.767 ns) + CELL(0.590 ns) = 2.357 ns; Loc. = LC_X17_Y6_N4; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.357 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.867 ns) 4.784 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 3 REG LC_X19_Y8_N8 4 " "Info: 3: + IC(1.560 ns) + CELL(0.867 ns) = 4.784 ns; Loc. = LC_X19_Y8_N8; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.427 ns" { sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 30.46 % ) " "Info: Total cell delay = 1.457 ns ( 30.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.327 ns ( 69.54 % ) " "Info: Total interconnect delay = 3.327 ns ( 69.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.784 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.784 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 1.767ns 1.560ns } { 0.000ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 266 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 266; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 2 REG LC_X19_Y8_N8 4 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X19_Y8_N8; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.784 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.784 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 1.767ns 1.560ns } { 0.000ns 0.590ns 0.867ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[8\] SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9~porta_address_reg0 10.520 ns memory " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[8\]\" through memory \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9~porta_address_reg0\" is 10.520 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK tt:inst1\|altpll:altpll_component\|_clk0 -1.833 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"tt:inst1\|altpll:altpll_component\|_clk0\" is -1.833 ns" {  } { { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 104 -360 -192 120 "CLK" "" } } } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 source 2.329 ns + Longest memory " "Info: + Longest clock path from clock \"tt:inst1\|altpll:altpll_component\|_clk0\" to source memory is 2.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tt:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 53; CLK Node = 'tt:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.722 ns) 2.329 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9~porta_address_reg0 2 MEM M4K_X13_Y8 4 " "Info: 2: + IC(1.607 ns) + CELL(0.722 ns) = 2.329 ns; Loc. = M4K_X13_Y8; Fanout = 4; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9~porta_address_reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 336 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 31.00 % ) " "Info: Total cell delay = 0.722 ns ( 31.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.00 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg0 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 336 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.374 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9~porta_address_reg0 1 MEM M4K_X13_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 4; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a9~porta_address_reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 336 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|q_a\[8\] 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|q_a\[8\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.308 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|q_a[8] } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.942 ns) + CELL(2.124 ns) 9.374 ns FOUT\[8\] 3 PIN PIN_78 0 " "Info: 3: + IC(2.942 ns) + CELL(2.124 ns) = 9.374 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'FOUT\[8\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.066 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|q_a[8] FOUT[8] } "NODE_NAME" } } { "DDS_ALL.bdf" "" { Schematic "E:/EDA/DDS_all/DDS_ALL.bdf" { { 152 928 1104 168 "FOUT\[9..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.432 ns ( 68.62 % ) " "Info: Total cell delay = 6.432 ns ( 68.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.942 ns ( 31.38 % ) " "Info: Total interconnect delay = 2.942 ns ( 31.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "9.374 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|q