dds_all.tan.qmsg

这个是相当不错的EDA编程

{ "Info" "ITDB_FULL_SLACK_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 memory SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1 memory SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1 11.59 ns " "Info: Slack time is 11.59 ns for clock \"tt:inst1\|altpll:altpll_component\|_clk0\" between source memory \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1\" and destination memory \"SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "15.909 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 15.909 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "16.666 ns + " "Info: + Setup relationship between source and destination is 16.666 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 14.833 ns " "Info: + Latch edge is 14.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination tt:inst1\|altpll:altpll_component\|_clk0 16.666 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"tt:inst1\|altpll:altpll_component\|_clk0\" is 16.666 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source tt:inst1\|altpll:altpll_component\|_clk0 16.666 ns -1.833 ns  50 " "Info: Clock period of Source clock \"tt:inst1\|altpll:altpll_component\|_clk0\" is 16.666 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 destination 2.315 ns + Shortest memory " "Info: + Shortest clock path from clock \"tt:inst1\|altpll:altpll_component\|_clk0\" to destination memory is 2.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tt:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 53; CLK Node = 'tt:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.708 ns) 2.315 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1 2 MEM M4K_X13_Y10 0 " "Info: 2: + IC(1.607 ns) + CELL(0.708 ns) = 2.315 ns; Loc. = M4K_X13_Y10; Fanout = 0; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 30.58 % ) " "Info: Total cell delay = 0.708 ns ( 30.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.42 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tt:inst1\|altpll:altpll_component\|_clk0 source 2.329 ns - Longest memory " "Info: - Longest clock path from clock \"tt:inst1\|altpll:altpll_component\|_clk0\" to source memory is 2.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tt:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 53; CLK Node = 'tt:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { tt:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/quartus/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.722 ns) 2.329 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1 2 MEM M4K_X13_Y10 1 " "Info: 2: + IC(1.607 ns) + CELL(0.722 ns) = 2.329 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 31.00 % ) " "Info: Total cell delay = 0.722 ns ( 31.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.00 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1 1 MEM M4K_X13_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_datain_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1 2 MEM M4K_X13_Y10 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y10; Fanout = 0; MEM Node = 'SIN_ROM:inst5\|altsyncram:altsyncram_component\|altsyncram_sq71:auto_generated\|altsyncram_kol2:altsyncram1\|ram_block3a2~porta_memory_reg1'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "db/altsyncram_kol2.tdf" "" { Text "E:/EDA/DDS_all/db/altsyncram_kol2.tdf" 112 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.315 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.708ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.329 ns" { tt:inst1|altpll:altpll_component|_clk0 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 } { 0.000ns 1.607ns } { 0.000ns 0.722ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.319 ns" { SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] register sld_hub:sld_hub_inst\|hub_tdo 65.26 MHz 15.324 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 65.26 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 15.324 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.401 ns + Longest register register " "Info: + Longest register to register delay is 7.401 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 1 REG LC_X21_Y9_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y9_N1; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.464 ns) + CELL(0.292 ns) 2.756 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]~209 2 COMB LC_X15_Y9_N9 2 " "Info: 2: + IC(2.464 ns) + CELL(0.292 ns) = 2.756 ns; Loc. = LC_X15_Y9_N9; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]~209'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.756 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.292 ns) 4.339 ns sld_hub:sld_hub_inst\|hub_tdo~980 3 COMB LC_X16_Y7_N6 1 " "Info: 3: + IC(1.291 ns) + CELL(0.292 ns) = 4.339 ns; Loc. = LC_X16_Y7_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~980'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.583 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~980 } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.550 ns) + CELL(0.590 ns) 6.479 ns sld_hub:sld_hub_inst\|hub_tdo~982 4 COMB LC_X18_Y8_N8 1 " "Info: 4: + IC(1.550 ns) + CELL(0.590 ns) = 6.479 ns; Loc. = LC_X18_Y8_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~982'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.140 ns" { sld_hub:sld_hub_inst|hub_tdo~980 sld_hub:sld_hub_inst|hub_tdo~982 } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.478 ns) 7.401 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LC_X18_Y8_N7 1 " "Info: 5: + IC(0.444 ns) + CELL(0.478 ns) = 7.401 ns; Loc. = LC_X18_Y8_N7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.922 ns" { sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.652 ns ( 22.32 % ) " "Info: Total cell delay = 1.652 ns ( 22.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.749 ns ( 77.68 % ) " "Info: Total interconnect delay = 5.749 ns ( 77.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "7.401 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~980 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "7.401 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~980 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.464ns 1.291ns 1.550ns 0.444ns } { 0.000ns 0.292ns 0.292ns 0.590ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 266 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 266; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X18_Y8_N7 1 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X18_Y8_N7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.272 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 266 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 266; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 2 REG LC_X21_Y9_N1 5 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X21_Y9_N1; Fanout = 5; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "d:/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "d:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/quartus/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "7.401 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~980 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "7.401 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~980 sld_hub:sld_hub_inst|hub_tdo~982 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.464ns 1.291ns 1.550ns 0.444ns } { 0.000ns 0.292ns 0.292ns 0.590ns 0.478ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}