dds_all.map.eqn

这个是相当不错的EDA编程

P2_q_b[8]_clock_0 = GND;
P2_q_b[8]_clock_1 = A1L5;
P2_q_b[8]_PORT_B_data_out = MEMORY(P2_q_b[8]_PORT_A_data_in_reg, P2_q_b[8]_PORT_B_data_in_reg, P2_q_b[8]_PORT_A_address_reg, P2_q_b[8]_PORT_B_address_reg, P2_q_b[8]_PORT_A_write_enable_reg, P2_q_b[8]_PORT_B_write_enable_reg, , , P2_q_b[8]_clock_0, P2_q_b[8]_clock_1, , , , );
P2_q_b[8] = P2_q_b[8]_PORT_B_data_out[0];


--P2_q_a[7] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[7]_PORT_A_data_in = VCC;
P2_q_a[7]_PORT_A_data_in_reg = DFFE(P2_q_a[7]_PORT_A_data_in, P2_q_a[7]_clock_0, , , );
P2_q_a[7]_PORT_B_data_in = Q2_ram_rom_data_reg[7];
P2_q_a[7]_PORT_B_data_in_reg = DFFE(P2_q_a[7]_PORT_B_data_in, P2_q_a[7]_clock_1, , , );
P2_q_a[7]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[7]_PORT_A_address_reg = DFFE(P2_q_a[7]_PORT_A_address, P2_q_a[7]_clock_0, , , );
P2_q_a[7]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[7]_PORT_B_address_reg = DFFE(P2_q_a[7]_PORT_B_address, P2_q_a[7]_clock_1, , , );
P2_q_a[7]_PORT_A_write_enable = GND;
P2_q_a[7]_PORT_A_write_enable_reg = DFFE(P2_q_a[7]_PORT_A_write_enable, P2_q_a[7]_clock_0, , , );
P2_q_a[7]_PORT_B_write_enable = Q2L53;
P2_q_a[7]_PORT_B_write_enable_reg = DFFE(P2_q_a[7]_PORT_B_write_enable, P2_q_a[7]_clock_1, , , );
P2_q_a[7]_clock_0 = GND;
P2_q_a[7]_clock_1 = A1L5;
P2_q_a[7]_PORT_A_data_out = MEMORY(P2_q_a[7]_PORT_A_data_in_reg, P2_q_a[7]_PORT_B_data_in_reg, P2_q_a[7]_PORT_A_address_reg, P2_q_a[7]_PORT_B_address_reg, P2_q_a[7]_PORT_A_write_enable_reg, P2_q_a[7]_PORT_B_write_enable_reg, , , P2_q_a[7]_clock_0, P2_q_a[7]_clock_1, , , , );
P2_q_a[7] = P2_q_a[7]_PORT_A_data_out[0];

--P2_q_b[7] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[7]
P2_q_b[7]_PORT_A_data_in = VCC;
P2_q_b[7]_PORT_A_data_in_reg = DFFE(P2_q_b[7]_PORT_A_data_in, P2_q_b[7]_clock_0, , , );
P2_q_b[7]_PORT_B_data_in = Q2_ram_rom_data_reg[7];
P2_q_b[7]_PORT_B_data_in_reg = DFFE(P2_q_b[7]_PORT_B_data_in, P2_q_b[7]_clock_1, , , );
P2_q_b[7]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[7]_PORT_A_address_reg = DFFE(P2_q_b[7]_PORT_A_address, P2_q_b[7]_clock_0, , , );
P2_q_b[7]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[7]_PORT_B_address_reg = DFFE(P2_q_b[7]_PORT_B_address, P2_q_b[7]_clock_1, , , );
P2_q_b[7]_PORT_A_write_enable = GND;
P2_q_b[7]_PORT_A_write_enable_reg = DFFE(P2_q_b[7]_PORT_A_write_enable, P2_q_b[7]_clock_0, , , );
P2_q_b[7]_PORT_B_write_enable = Q2L53;
P2_q_b[7]_PORT_B_write_enable_reg = DFFE(P2_q_b[7]_PORT_B_write_enable, P2_q_b[7]_clock_1, , , );
P2_q_b[7]_clock_0 = GND;
P2_q_b[7]_clock_1 = A1L5;
P2_q_b[7]_PORT_B_data_out = MEMORY(P2_q_b[7]_PORT_A_data_in_reg, P2_q_b[7]_PORT_B_data_in_reg, P2_q_b[7]_PORT_A_address_reg, P2_q_b[7]_PORT_B_address_reg, P2_q_b[7]_PORT_A_write_enable_reg, P2_q_b[7]_PORT_B_write_enable_reg, , , P2_q_b[7]_clock_0, P2_q_b[7]_clock_1, , , , );
P2_q_b[7] = P2_q_b[7]_PORT_B_data_out[0];


--P2_q_a[6] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[6]_PORT_A_data_in = VCC;
P2_q_a[6]_PORT_A_data_in_reg = DFFE(P2_q_a[6]_PORT_A_data_in, P2_q_a[6]_clock_0, , , );
P2_q_a[6]_PORT_B_data_in = Q2_ram_rom_data_reg[6];
P2_q_a[6]_PORT_B_data_in_reg = DFFE(P2_q_a[6]_PORT_B_data_in, P2_q_a[6]_clock_1, , , );
P2_q_a[6]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[6]_PORT_A_address_reg = DFFE(P2_q_a[6]_PORT_A_address, P2_q_a[6]_clock_0, , , );
P2_q_a[6]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[6]_PORT_B_address_reg = DFFE(P2_q_a[6]_PORT_B_address, P2_q_a[6]_clock_1, , , );
P2_q_a[6]_PORT_A_write_enable = GND;
P2_q_a[6]_PORT_A_write_enable_reg = DFFE(P2_q_a[6]_PORT_A_write_enable, P2_q_a[6]_clock_0, , , );
P2_q_a[6]_PORT_B_write_enable = Q2L53;
P2_q_a[6]_PORT_B_write_enable_reg = DFFE(P2_q_a[6]_PORT_B_write_enable, P2_q_a[6]_clock_1, , , );
P2_q_a[6]_clock_0 = GND;
P2_q_a[6]_clock_1 = A1L5;
P2_q_a[6]_PORT_A_data_out = MEMORY(P2_q_a[6]_PORT_A_data_in_reg, P2_q_a[6]_PORT_B_data_in_reg, P2_q_a[6]_PORT_A_address_reg, P2_q_a[6]_PORT_B_address_reg, P2_q_a[6]_PORT_A_write_enable_reg, P2_q_a[6]_PORT_B_write_enable_reg, , , P2_q_a[6]_clock_0, P2_q_a[6]_clock_1, , , , );
P2_q_a[6] = P2_q_a[6]_PORT_A_data_out[0];

--P2_q_b[6] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[6]
P2_q_b[6]_PORT_A_data_in = VCC;
P2_q_b[6]_PORT_A_data_in_reg = DFFE(P2_q_b[6]_PORT_A_data_in, P2_q_b[6]_clock_0, , , );
P2_q_b[6]_PORT_B_data_in = Q2_ram_rom_data_reg[6];
P2_q_b[6]_PORT_B_data_in_reg = DFFE(P2_q_b[6]_PORT_B_data_in, P2_q_b[6]_clock_1, , , );
P2_q_b[6]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[6]_PORT_A_address_reg = DFFE(P2_q_b[6]_PORT_A_address, P2_q_b[6]_clock_0, , , );
P2_q_b[6]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[6]_PORT_B_address_reg = DFFE(P2_q_b[6]_PORT_B_address, P2_q_b[6]_clock_1, , , );
P2_q_b[6]_PORT_A_write_enable = GND;
P2_q_b[6]_PORT_A_write_enable_reg = DFFE(P2_q_b[6]_PORT_A_write_enable, P2_q_b[6]_clock_0, , , );
P2_q_b[6]_PORT_B_write_enable = Q2L53;
P2_q_b[6]_PORT_B_write_enable_reg = DFFE(P2_q_b[6]_PORT_B_write_enable, P2_q_b[6]_clock_1, , , );
P2_q_b[6]_clock_0 = GND;
P2_q_b[6]_clock_1 = A1L5;
P2_q_b[6]_PORT_B_data_out = MEMORY(P2_q_b[6]_PORT_A_data_in_reg, P2_q_b[6]_PORT_B_data_in_reg, P2_q_b[6]_PORT_A_address_reg, P2_q_b[6]_PORT_B_address_reg, P2_q_b[6]_PORT_A_write_enable_reg, P2_q_b[6]_PORT_B_write_enable_reg, , , P2_q_b[6]_clock_0, P2_q_b[6]_clock_1, , , , );
P2_q_b[6] = P2_q_b[6]_PORT_B_data_out[0];


--P2_q_a[5] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[5]_PORT_A_data_in = VCC;
P2_q_a[5]_PORT_A_data_in_reg = DFFE(P2_q_a[5]_PORT_A_data_in, P2_q_a[5]_clock_0, , , );
P2_q_a[5]_PORT_B_data_in = Q2_ram_rom_data_reg[5];
P2_q_a[5]_PORT_B_data_in_reg = DFFE(P2_q_a[5]_PORT_B_data_in, P2_q_a[5]_clock_1, , , );
P2_q_a[5]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[5]_PORT_A_address_reg = DFFE(P2_q_a[5]_PORT_A_address, P2_q_a[5]_clock_0, , , );
P2_q_a[5]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[5]_PORT_B_address_reg = DFFE(P2_q_a[5]_PORT_B_address, P2_q_a[5]_clock_1, , , );
P2_q_a[5]_PORT_A_write_enable = GND;
P2_q_a[5]_PORT_A_write_enable_reg = DFFE(P2_q_a[5]_PORT_A_write_enable, P2_q_a[5]_clock_0, , , );
P2_q_a[5]_PORT_B_write_enable = Q2L53;
P2_q_a[5]_PORT_B_write_enable_reg = DFFE(P2_q_a[5]_PORT_B_write_enable, P2_q_a[5]_clock_1, , , );
P2_q_a[5]_clock_0 = GND;
P2_q_a[5]_clock_1 = A1L5;
P2_q_a[5]_PORT_A_data_out = MEMORY(P2_q_a[5]_PORT_A_data_in_reg, P2_q_a[5]_PORT_B_data_in_reg, P2_q_a[5]_PORT_A_address_reg, P2_q_a[5]_PORT_B_address_reg, P2_q_a[5]_PORT_A_write_enable_reg, P2_q_a[5]_PORT_B_write_enable_reg, , , P2_q_a[5]_clock_0, P2_q_a[5]_clock_1, , , , );
P2_q_a[5] = P2_q_a[5]_PORT_A_data_out[0];

--P2_q_b[5] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[5]
P2_q_b[5]_PORT_A_data_in = VCC;
P2_q_b[5]_PORT_A_data_in_reg = DFFE(P2_q_b[5]_PORT_A_data_in, P2_q_b[5]_clock_0, , , );
P2_q_b[5]_PORT_B_data_in = Q2_ram_rom_data_reg[5];
P2_q_b[5]_PORT_B_data_in_reg = DFFE(P2_q_b[5]_PORT_B_data_in, P2_q_b[5]_clock_1, , , );
P2_q_b[5]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[5]_PORT_A_address_reg = DFFE(P2_q_b[5]_PORT_A_address, P2_q_b[5]_clock_0, , , );
P2_q_b[5]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[5]_PORT_B_address_reg = DFFE(P2_q_b[5]_PORT_B_address, P2_q_b[5]_clock_1, , , );
P2_q_b[5]_PORT_A_write_enable = GND;
P2_q_b[5]_PORT_A_write_enable_reg = DFFE(P2_q_b[5]_PORT_A_write_enable, P2_q_b[5]_clock_0, , , );
P2_q_b[5]_PORT_B_write_enable = Q2L53;
P2_q_b[5]_PORT_B_write_enable_reg = DFFE(P2_q_b[5]_PORT_B_write_enable, P2_q_b[5]_clock_1, , , );
P2_q_b[5]_clock_0 = GND;
P2_q_b[5]_clock_1 = A1L5;
P2_q_b[5]_PORT_B_data_out = MEMORY(P2_q_b[5]_PORT_A_data_in_reg, P2_q_b[5]_PORT_B_data_in_reg, P2_q_b[5]_PORT_A_address_reg, P2_q_b[5]_PORT_B_address_reg, P2_q_b[5]_PORT_A_write_enable_reg, P2_q_b[5]_PORT_B_write_enable_reg, , , P2_q_b[5]_clock_0, P2_q_b[5]_clock_1, , , , );
P2_q_b[5] = P2_q_b[5]_PORT_B_data_out[0];


--P2_q_a[4] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[4]_PORT_A_data_in = VCC;
P2_q_a[4]_PORT_A_data_in_reg = DFFE(P2_q_a[4]_PORT_A_data_in, P2_q_a[4]_clock_0, , , );
P2_q_a[4]_PORT_B_data_in = Q2_ram_rom_data_reg[4];
P2_q_a[4]_PORT_B_data_in_reg = DFFE(P2_q_a[4]_PORT_B_data_in, P2_q_a[4]_clock_1, , , );
P2_q_a[4]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[4]_PORT_A_address_reg = DFFE(P2_q_a[4]_PORT_A_address, P2_q_a[4]_clock_0, , , );
P2_q_a[4]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[4]_PORT_B_address_reg = DFFE(P2_q_a[4]_PORT_B_address, P2_q_a[4]_clock_1, , , );
P2_q_a[4]_PORT_A_write_enable = GND;
P2_q_a[4]_PORT_A_write_enable_reg = DFFE(P2_q_a[4]_PORT_A_write_enable, P2_q_a[4]_clock_0, , , );
P2_q_a[4]_PORT_B_write_enable = Q2L53;
P2_q_a[4]_PORT_B_write_enable_reg = DFFE(P2_q_a[4]_PORT_B_write_enable, P2_q_a[4]_clock_1, , , );
P2_q_a[4]_clock_0 = GND;
P2_q_a[4]_clock_1 = A1L5;
P2_q_a[4]_PORT_A_data_out = MEMORY(P2_q_a[4]_PORT_A_data_in_reg, P2_q_a[4]_PORT_B_data_in_reg, P2_q_a[4]_PORT_A_address_reg, P2_q_a[4]_PORT_B_address_reg, P2_q_a[4]_PORT_A_write_enable_reg, P2_q_a[4]_PORT_B_write_enable_reg, , , P2_q_a[4]_clock_0, P2_q_a[4]_clock_1, , , , );
P2_q_a[4] = P2_q_a[4]_PORT_A_data_out[0];

--P2_q_b[4] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[4]
P2_q_b[4]_PORT_A_data_in = VCC;
P2_q_b[4]_PORT_A_data_in_reg = DFFE(P2_q_b[4]_PORT_A_data_in, P2_q_b[4]_clock_0, , , );
P2_q_b[4]_PORT_B_data_in = Q2_ram_rom_data_reg[4];
P2_q_b[4]_PORT_B_data_in_reg = DFFE(P2_q_b[4]_PORT_B_data_in, P2_q_b[4]_clock_1, , , );
P2_q_b[4]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[4]_PORT_A_address_reg = DFFE(P2_q_b[4]_PORT_A_address, P2_q_b[4]_clock_0, , , );
P2_q_b[4]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[4]_PORT_B_address_reg = DFFE(P2_q_b[4]_PORT_B_address, P2_q_b[4]_clock_1, , , );
P2_q_b[4]_PORT_A_write_enable = GND;
P2_q_b[4]_PORT_A_write_enable_reg = DFFE(P2_q_b[4]_PORT_A_write_enable, P2_q_b[4]_clock_0, , , );