dds_all.map.eqn

这个是相当不错的EDA编程

P1_q_b[2]_PORT_B_data_out = MEMORY(P1_q_b[2]_PORT_A_data_in_reg, P1_q_b[2]_PORT_B_data_in_reg, P1_q_b[2]_PORT_A_address_reg, P1_q_b[2]_PORT_B_address_reg, P1_q_b[2]_PORT_A_write_enable_reg, P1_q_b[2]_PORT_B_write_enable_reg, , , P1_q_b[2]_clock_0, P1_q_b[2]_clock_1, , , , );
P1_q_b[2] = P1_q_b[2]_PORT_B_data_out[0];


--P1_q_a[1] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[1]_PORT_A_data_in = VCC;
P1_q_a[1]_PORT_A_data_in_reg = DFFE(P1_q_a[1]_PORT_A_data_in, P1_q_a[1]_clock_0, , , );
P1_q_a[1]_PORT_B_data_in = Q1_ram_rom_data_reg[1];
P1_q_a[1]_PORT_B_data_in_reg = DFFE(P1_q_a[1]_PORT_B_data_in, P1_q_a[1]_clock_1, , , );
P1_q_a[1]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_a[1]_PORT_A_address_reg = DFFE(P1_q_a[1]_PORT_A_address, P1_q_a[1]_clock_0, , , );
P1_q_a[1]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_a[1]_PORT_B_address_reg = DFFE(P1_q_a[1]_PORT_B_address, P1_q_a[1]_clock_1, , , );
P1_q_a[1]_PORT_A_write_enable = GND;
P1_q_a[1]_PORT_A_write_enable_reg = DFFE(P1_q_a[1]_PORT_A_write_enable, P1_q_a[1]_clock_0, , , );
P1_q_a[1]_PORT_B_write_enable = Q1L53;
P1_q_a[1]_PORT_B_write_enable_reg = DFFE(P1_q_a[1]_PORT_B_write_enable, P1_q_a[1]_clock_1, , , );
P1_q_a[1]_clock_0 = L1__clk0;
P1_q_a[1]_clock_1 = A1L5;
P1_q_a[1]_PORT_A_data_out = MEMORY(P1_q_a[1]_PORT_A_data_in_reg, P1_q_a[1]_PORT_B_data_in_reg, P1_q_a[1]_PORT_A_address_reg, P1_q_a[1]_PORT_B_address_reg, P1_q_a[1]_PORT_A_write_enable_reg, P1_q_a[1]_PORT_B_write_enable_reg, , , P1_q_a[1]_clock_0, P1_q_a[1]_clock_1, , , , );
P1_q_a[1] = P1_q_a[1]_PORT_A_data_out[0];

--P1_q_b[1] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[1]
P1_q_b[1]_PORT_A_data_in = VCC;
P1_q_b[1]_PORT_A_data_in_reg = DFFE(P1_q_b[1]_PORT_A_data_in, P1_q_b[1]_clock_0, , , );
P1_q_b[1]_PORT_B_data_in = Q1_ram_rom_data_reg[1];
P1_q_b[1]_PORT_B_data_in_reg = DFFE(P1_q_b[1]_PORT_B_data_in, P1_q_b[1]_clock_1, , , );
P1_q_b[1]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_b[1]_PORT_A_address_reg = DFFE(P1_q_b[1]_PORT_A_address, P1_q_b[1]_clock_0, , , );
P1_q_b[1]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_b[1]_PORT_B_address_reg = DFFE(P1_q_b[1]_PORT_B_address, P1_q_b[1]_clock_1, , , );
P1_q_b[1]_PORT_A_write_enable = GND;
P1_q_b[1]_PORT_A_write_enable_reg = DFFE(P1_q_b[1]_PORT_A_write_enable, P1_q_b[1]_clock_0, , , );
P1_q_b[1]_PORT_B_write_enable = Q1L53;
P1_q_b[1]_PORT_B_write_enable_reg = DFFE(P1_q_b[1]_PORT_B_write_enable, P1_q_b[1]_clock_1, , , );
P1_q_b[1]_clock_0 = L1__clk0;
P1_q_b[1]_clock_1 = A1L5;
P1_q_b[1]_PORT_B_data_out = MEMORY(P1_q_b[1]_PORT_A_data_in_reg, P1_q_b[1]_PORT_B_data_in_reg, P1_q_b[1]_PORT_A_address_reg, P1_q_b[1]_PORT_B_address_reg, P1_q_b[1]_PORT_A_write_enable_reg, P1_q_b[1]_PORT_B_write_enable_reg, , , P1_q_b[1]_clock_0, P1_q_b[1]_clock_1, , , , );
P1_q_b[1] = P1_q_b[1]_PORT_B_data_out[0];


--P1_q_a[0] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[0]_PORT_A_data_in = VCC;
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_data_in = Q1_ram_rom_data_reg[0];
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , );
P1_q_a[0]_PORT_B_write_enable = Q1L53;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = L1__clk0;
P1_q_a[0]_clock_1 = A1L5;
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, , , , );
P1_q_a[0] = P1_q_a[0]_PORT_A_data_out[0];

--P1_q_b[0] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[0]
P1_q_b[0]_PORT_A_data_in = VCC;
P1_q_b[0]_PORT_A_data_in_reg = DFFE(P1_q_b[0]_PORT_A_data_in, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_data_in = Q1_ram_rom_data_reg[0];
P1_q_b[0]_PORT_B_data_in_reg = DFFE(P1_q_b[0]_PORT_B_data_in, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_b[0]_PORT_A_address_reg = DFFE(P1_q_b[0]_PORT_A_address, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_b[0]_PORT_B_address_reg = DFFE(P1_q_b[0]_PORT_B_address, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_PORT_A_write_enable = GND;
P1_q_b[0]_PORT_A_write_enable_reg = DFFE(P1_q_b[0]_PORT_A_write_enable, P1_q_b[0]_clock_0, , , );
P1_q_b[0]_PORT_B_write_enable = Q1L53;
P1_q_b[0]_PORT_B_write_enable_reg = DFFE(P1_q_b[0]_PORT_B_write_enable, P1_q_b[0]_clock_1, , , );
P1_q_b[0]_clock_0 = L1__clk0;
P1_q_b[0]_clock_1 = A1L5;
P1_q_b[0]_PORT_B_data_out = MEMORY(P1_q_b[0]_PORT_A_data_in_reg, P1_q_b[0]_PORT_B_data_in_reg, P1_q_b[0]_PORT_A_address_reg, P1_q_b[0]_PORT_B_address_reg, P1_q_b[0]_PORT_A_write_enable_reg, P1_q_b[0]_PORT_B_write_enable_reg, , , P1_q_b[0]_clock_0, P1_q_b[0]_clock_1, , , , );
P1_q_b[0] = P1_q_b[0]_PORT_B_data_out[0];


--P2_q_a[9] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[9]_PORT_A_data_in = VCC;
P2_q_a[9]_PORT_A_data_in_reg = DFFE(P2_q_a[9]_PORT_A_data_in, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_data_in = Q2_ram_rom_data_reg[9];
P2_q_a[9]_PORT_B_data_in_reg = DFFE(P2_q_a[9]_PORT_B_data_in, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[9]_PORT_A_address_reg = DFFE(P2_q_a[9]_PORT_A_address, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[9]_PORT_B_address_reg = DFFE(P2_q_a[9]_PORT_B_address, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_write_enable = GND;
P2_q_a[9]_PORT_A_write_enable_reg = DFFE(P2_q_a[9]_PORT_A_write_enable, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_write_enable = Q2L53;
P2_q_a[9]_PORT_B_write_enable_reg = DFFE(P2_q_a[9]_PORT_B_write_enable, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_clock_0 = GND;
P2_q_a[9]_clock_1 = A1L5;
P2_q_a[9]_PORT_A_data_out = MEMORY(P2_q_a[9]_PORT_A_data_in_reg, P2_q_a[9]_PORT_B_data_in_reg, P2_q_a[9]_PORT_A_address_reg, P2_q_a[9]_PORT_B_address_reg, P2_q_a[9]_PORT_A_write_enable_reg, P2_q_a[9]_PORT_B_write_enable_reg, , , P2_q_a[9]_clock_0, P2_q_a[9]_clock_1, , , , );
P2_q_a[9] = P2_q_a[9]_PORT_A_data_out[0];

--P2_q_b[9] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[9]
P2_q_b[9]_PORT_A_data_in = VCC;
P2_q_b[9]_PORT_A_data_in_reg = DFFE(P2_q_b[9]_PORT_A_data_in, P2_q_b[9]_clock_0, , , );
P2_q_b[9]_PORT_B_data_in = Q2_ram_rom_data_reg[9];
P2_q_b[9]_PORT_B_data_in_reg = DFFE(P2_q_b[9]_PORT_B_data_in, P2_q_b[9]_clock_1, , , );
P2_q_b[9]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[9]_PORT_A_address_reg = DFFE(P2_q_b[9]_PORT_A_address, P2_q_b[9]_clock_0, , , );
P2_q_b[9]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[9]_PORT_B_address_reg = DFFE(P2_q_b[9]_PORT_B_address, P2_q_b[9]_clock_1, , , );
P2_q_b[9]_PORT_A_write_enable = GND;
P2_q_b[9]_PORT_A_write_enable_reg = DFFE(P2_q_b[9]_PORT_A_write_enable, P2_q_b[9]_clock_0, , , );
P2_q_b[9]_PORT_B_write_enable = Q2L53;
P2_q_b[9]_PORT_B_write_enable_reg = DFFE(P2_q_b[9]_PORT_B_write_enable, P2_q_b[9]_clock_1, , , );
P2_q_b[9]_clock_0 = GND;
P2_q_b[9]_clock_1 = A1L5;
P2_q_b[9]_PORT_B_data_out = MEMORY(P2_q_b[9]_PORT_A_data_in_reg, P2_q_b[9]_PORT_B_data_in_reg, P2_q_b[9]_PORT_A_address_reg, P2_q_b[9]_PORT_B_address_reg, P2_q_b[9]_PORT_A_write_enable_reg, P2_q_b[9]_PORT_B_write_enable_reg, , , P2_q_b[9]_clock_0, P2_q_b[9]_clock_1, , , , );
P2_q_b[9] = P2_q_b[9]_PORT_B_data_out[0];


--P2_q_a[8] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[8]_PORT_A_data_in = VCC;
P2_q_a[8]_PORT_A_data_in_reg = DFFE(P2_q_a[8]_PORT_A_data_in, P2_q_a[8]_clock_0, , , );
P2_q_a[8]_PORT_B_data_in = Q2_ram_rom_data_reg[8];
P2_q_a[8]_PORT_B_data_in_reg = DFFE(P2_q_a[8]_PORT_B_data_in, P2_q_a[8]_clock_1, , , );
P2_q_a[8]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[8]_PORT_A_address_reg = DFFE(P2_q_a[8]_PORT_A_address, P2_q_a[8]_clock_0, , , );
P2_q_a[8]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[8]_PORT_B_address_reg = DFFE(P2_q_a[8]_PORT_B_address, P2_q_a[8]_clock_1, , , );
P2_q_a[8]_PORT_A_write_enable = GND;
P2_q_a[8]_PORT_A_write_enable_reg = DFFE(P2_q_a[8]_PORT_A_write_enable, P2_q_a[8]_clock_0, , , );
P2_q_a[8]_PORT_B_write_enable = Q2L53;
P2_q_a[8]_PORT_B_write_enable_reg = DFFE(P2_q_a[8]_PORT_B_write_enable, P2_q_a[8]_clock_1, , , );
P2_q_a[8]_clock_0 = GND;
P2_q_a[8]_clock_1 = A1L5;
P2_q_a[8]_PORT_A_data_out = MEMORY(P2_q_a[8]_PORT_A_data_in_reg, P2_q_a[8]_PORT_B_data_in_reg, P2_q_a[8]_PORT_A_address_reg, P2_q_a[8]_PORT_B_address_reg, P2_q_a[8]_PORT_A_write_enable_reg, P2_q_a[8]_PORT_B_write_enable_reg, , , P2_q_a[8]_clock_0, P2_q_a[8]_clock_1, , , , );
P2_q_a[8] = P2_q_a[8]_PORT_A_data_out[0];

--P2_q_b[8] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[8]
P2_q_b[8]_PORT_A_data_in = VCC;
P2_q_b[8]_PORT_A_data_in_reg = DFFE(P2_q_b[8]_PORT_A_data_in, P2_q_b[8]_clock_0, , , );
P2_q_b[8]_PORT_B_data_in = Q2_ram_rom_data_reg[8];
P2_q_b[8]_PORT_B_data_in_reg = DFFE(P2_q_b[8]_PORT_B_data_in, P2_q_b[8]_clock_1, , , );
P2_q_b[8]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[8]_PORT_A_address_reg = DFFE(P2_q_b[8]_PORT_A_address, P2_q_b[8]_clock_0, , , );
P2_q_b[8]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[8]_PORT_B_address_reg = DFFE(P2_q_b[8]_PORT_B_address, P2_q_b[8]_clock_1, , , );
P2_q_b[8]_PORT_A_write_enable = GND;
P2_q_b[8]_PORT_A_write_enable_reg = DFFE(P2_q_b[8]_PORT_A_write_enable, P2_q_b[8]_clock_0, , , );
P2_q_b[8]_PORT_B_write_enable = Q2L53;
P2_q_b[8]_PORT_B_write_enable_reg = DFFE(P2_q_b[8]_PORT_B_write_enable, P2_q_b[8]_clock_1, , , );