dds_all.tan.summary

来自「这个是相当不错的EDA编程」· SUMMARY 代码 · 共 107 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.451 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.520 ns
From           : SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg9
To             : FOUT[8]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.646 ns
From           : altera_internal_jtag
To             : SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.241 ns
From           : SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_address_reg9
To             : FOUT[2]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'tt:inst1|altpll:altpll_component|_clk0'
Slack          : 11.590 ns
Required Time  : 60.00 MHz ( period = 16.666 ns )
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1
To             : SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1
From Clock     : tt:inst1|altpll:altpll_component|_clk0
To Clock       : tt:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 65.26 MHz ( period = 15.324 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'tt:inst1|altpll:altpll_component|_clk0'
Slack          : 4.928 ns
Required Time  : 60.00 MHz ( period = 16.666 ns )
Actual Time    : N/A
From           : SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1
To             : SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1
From Clock     : tt:inst1|altpll:altpll_component|_clk0
To Clock       : tt:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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