dds_vhdl.tan.rpt

这个是相当不错的EDA编程

; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                 ; To                                                                       ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 7.291 ns                         ; PWORD[1]                                                                                                                             ; REG10B:u5|DOUT[9]                                                        ;                              ; CLK                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 13.481 ns                        ; SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a9~porta_address_reg9 ; FOUT[9]                                                                  ; CLK                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 5.000 ns                         ; CLK                                                                                                                                  ; clK20M                                                                   ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.370 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                         ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 11.049 ns                        ; SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a6~porta_address_reg9 ; FOUT[3]                                                                  ; CLK                          ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                             ; altera_reserved_tdo                                                      ;                              ;                              ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 110.50 MHz ( period = 9.050 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                   ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                        ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 134.01 MHz ( period = 7.462 ns ) ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg9 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                    ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                      ;                                                                          ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                            ; To                                                                                                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg0                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg1                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg2                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg3                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg4                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg5                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg6                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg7                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 134.01 MHz ( period = 7.462 ns )                    ; SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|ram_block3a4~porta_address_reg8                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;