dds_all.fit.eqn

这个是相当不错的EDA编程

--P1_q_a[7] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[7] at M4K_X13_Y11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 2, Port B Depth: 1024, Port B Width: 2
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[7]_PORT_A_data_in_reg = DFFE(P1_q_a[7]_PORT_A_data_in, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[7], Q1_ram_rom_data_reg[5]);
P1_q_a[7]_PORT_B_data_in_reg = DFFE(P1_q_a[7]_PORT_B_data_in, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_a[7]_PORT_A_address_reg = DFFE(P1_q_a[7]_PORT_A_address, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_a[7]_PORT_B_address_reg = DFFE(P1_q_a[7]_PORT_B_address, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_write_enable = GND;
P1_q_a[7]_PORT_A_write_enable_reg = DFFE(P1_q_a[7]_PORT_A_write_enable, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_write_enable = Q1L53;
P1_q_a[7]_PORT_B_write_enable_reg = DFFE(P1_q_a[7]_PORT_B_write_enable, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_clock_0 = GLOBAL(L1__clk0);
P1_q_a[7]_clock_1 = GLOBAL(A1L5);
P1_q_a[7]_PORT_A_data_out = MEMORY(P1_q_a[7]_PORT_A_data_in_reg, P1_q_a[7]_PORT_B_data_in_reg, P1_q_a[7]_PORT_A_address_reg, P1_q_a[7]_PORT_B_address_reg, P1_q_a[7]_PORT_A_write_enable_reg, P1_q_a[7]_PORT_B_write_enable_reg, , , P1_q_a[7]_clock_0, P1_q_a[7]_clock_1, , , , );
P1_q_a[7] = P1_q_a[7]_PORT_A_data_out[0];

--P1_q_b[7] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[7] at M4K_X13_Y11
P1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_b[7]_PORT_A_data_in_reg = DFFE(P1_q_b[7]_PORT_A_data_in, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[7], Q1_ram_rom_data_reg[5]);
P1_q_b[7]_PORT_B_data_in_reg = DFFE(P1_q_b[7]_PORT_B_data_in, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_b[7]_PORT_A_address_reg = DFFE(P1_q_b[7]_PORT_A_address, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_b[7]_PORT_B_address_reg = DFFE(P1_q_b[7]_PORT_B_address, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_PORT_A_write_enable = GND;
P1_q_b[7]_PORT_A_write_enable_reg = DFFE(P1_q_b[7]_PORT_A_write_enable, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_write_enable = Q1L53;
P1_q_b[7]_PORT_B_write_enable_reg = DFFE(P1_q_b[7]_PORT_B_write_enable, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_clock_0 = GLOBAL(L1__clk0);
P1_q_b[7]_clock_1 = GLOBAL(A1L5);
P1_q_b[7]_PORT_B_data_out = MEMORY(P1_q_b[7]_PORT_A_data_in_reg, P1_q_b[7]_PORT_B_data_in_reg, P1_q_b[7]_PORT_A_address_reg, P1_q_b[7]_PORT_B_address_reg, P1_q_b[7]_PORT_A_write_enable_reg, P1_q_b[7]_PORT_B_write_enable_reg, , , P1_q_b[7]_clock_0, P1_q_b[7]_clock_1, , , , );
P1_q_b[7] = P1_q_b[7]_PORT_B_data_out[0];

--P1_q_a[5] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[5] at M4K_X13_Y11
P1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[7]_PORT_A_data_in_reg = DFFE(P1_q_a[7]_PORT_A_data_in, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[7], Q1_ram_rom_data_reg[5]);
P1_q_a[7]_PORT_B_data_in_reg = DFFE(P1_q_a[7]_PORT_B_data_in, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_a[7]_PORT_A_address_reg = DFFE(P1_q_a[7]_PORT_A_address, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_a[7]_PORT_B_address_reg = DFFE(P1_q_a[7]_PORT_B_address, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_PORT_A_write_enable = GND;
P1_q_a[7]_PORT_A_write_enable_reg = DFFE(P1_q_a[7]_PORT_A_write_enable, P1_q_a[7]_clock_0, , , );
P1_q_a[7]_PORT_B_write_enable = Q1L53;
P1_q_a[7]_PORT_B_write_enable_reg = DFFE(P1_q_a[7]_PORT_B_write_enable, P1_q_a[7]_clock_1, , , );
P1_q_a[7]_clock_0 = GLOBAL(L1__clk0);
P1_q_a[7]_clock_1 = GLOBAL(A1L5);
P1_q_a[7]_PORT_A_data_out = MEMORY(P1_q_a[7]_PORT_A_data_in_reg, P1_q_a[7]_PORT_B_data_in_reg, P1_q_a[7]_PORT_A_address_reg, P1_q_a[7]_PORT_B_address_reg, P1_q_a[7]_PORT_A_write_enable_reg, P1_q_a[7]_PORT_B_write_enable_reg, , , P1_q_a[7]_clock_0, P1_q_a[7]_clock_1, , , , );
P1_q_a[5] = P1_q_a[7]_PORT_A_data_out[1];

--P1_q_b[5] is SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[5] at M4K_X13_Y11
P1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_b[7]_PORT_A_data_in_reg = DFFE(P1_q_b[7]_PORT_A_data_in, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_data_in = BUS(Q1_ram_rom_data_reg[7], Q1_ram_rom_data_reg[5]);
P1_q_b[7]_PORT_B_data_in_reg = DFFE(P1_q_b[7]_PORT_B_data_in, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P1_q_b[7]_PORT_A_address_reg = DFFE(P1_q_b[7]_PORT_A_address, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_address = BUS(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3], T1_safe_q[4], T1_safe_q[5], T1_safe_q[6], T1_safe_q[7], T1_safe_q[8], T1_safe_q[9]);
P1_q_b[7]_PORT_B_address_reg = DFFE(P1_q_b[7]_PORT_B_address, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_PORT_A_write_enable = GND;
P1_q_b[7]_PORT_A_write_enable_reg = DFFE(P1_q_b[7]_PORT_A_write_enable, P1_q_b[7]_clock_0, , , );
P1_q_b[7]_PORT_B_write_enable = Q1L53;
P1_q_b[7]_PORT_B_write_enable_reg = DFFE(P1_q_b[7]_PORT_B_write_enable, P1_q_b[7]_clock_1, , , );
P1_q_b[7]_clock_0 = GLOBAL(L1__clk0);
P1_q_b[7]_clock_1 = GLOBAL(A1L5);
P1_q_b[7]_PORT_B_data_out = MEMORY(P1_q_b[7]_PORT_A_data_in_reg, P1_q_b[7]_PORT_B_data_in_reg, P1_q_b[7]_PORT_A_address_reg, P1_q_b[7]_PORT_B_address_reg, P1_q_b[7]_PORT_A_write_enable_reg, P1_q_b[7]_PORT_B_write_enable_reg, , , P1_q_b[7]_clock_0, P1_q_b[7]_clock_1, , , , );
P1_q_b[5] = P1_q_b[7]_PORT_B_data_out[1];


--P2_q_a[9] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9] at M4K_X13_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
P2_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P2_q_a[9]_PORT_A_data_in_reg = DFFE(P2_q_a[9]_PORT_A_data_in, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_data_in = BUS(Q2_ram_rom_data_reg[9], Q2_ram_rom_data_reg[5], Q2_ram_rom_data_reg[3], Q2_ram_rom_data_reg[2]);
P2_q_a[9]_PORT_B_data_in_reg = DFFE(P2_q_a[9]_PORT_B_data_in, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[9]_PORT_A_address_reg = DFFE(P2_q_a[9]_PORT_A_address, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[9]_PORT_B_address_reg = DFFE(P2_q_a[9]_PORT_B_address, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_write_enable = GND;
P2_q_a[9]_PORT_A_write_enable_reg = DFFE(P2_q_a[9]_PORT_A_write_enable, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_write_enable = Q2L53;
P2_q_a[9]_PORT_B_write_enable_reg = DFFE(P2_q_a[9]_PORT_B_write_enable, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_clock_0 = GND;
P2_q_a[9]_clock_1 = GLOBAL(A1L5);
P2_q_a[9]_PORT_A_data_out = MEMORY(P2_q_a[9]_PORT_A_data_in_reg, P2_q_a[9]_PORT_B_data_in_reg, P2_q_a[9]_PORT_A_address_reg, P2_q_a[9]_PORT_B_address_reg, P2_q_a[9]_PORT_A_write_enable_reg, P2_q_a[9]_PORT_B_write_enable_reg, , , P2_q_a[9]_clock_0, P2_q_a[9]_clock_1, , , , );
P2_q_a[9] = P2_q_a[9]_PORT_A_data_out[0];

--P2_q_b[9] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_b[9] at M4K_X13_Y6
P2_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P2_q_b[9]_PORT_A_data_in_reg = DFFE(P2_q_b[9]_PORT_A_data_in, P2_q_b[9]_clock_0, , , );
P2_q_b[9]_PORT_B_data_in = BUS(Q2_ram_rom_data_reg[9], Q2_ram_rom_data_reg[5], Q2_ram_rom_data_reg[3], Q2_ram_rom_data_reg[2]);
P2_q_b[9]_PORT_B_data_in_reg = DFFE(P2_q_b[9]_PORT_B_data_in, P2_q_b[9]_clock_1, , , );
P2_q_b[9]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_b[9]_PORT_A_address_reg = DFFE(P2_q_b[9]_PORT_A_address, P2_q_b[9]_clock_0, , , );
P2_q_b[9]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_b[9]_PORT_B_address_reg = DFFE(P2_q_b[9]_PORT_B_address, P2_q_b[9]_clock_1, , , );
P2_q_b[9]_PORT_A_write_enable = GND;
P2_q_b[9]_PORT_A_write_enable_reg = DFFE(P2_q_b[9]_PORT_A_write_enable, P2_q_b[9]_clock_0, , , );
P2_q_b[9]_PORT_B_write_enable = Q2L53;
P2_q_b[9]_PORT_B_write_enable_reg = DFFE(P2_q_b[9]_PORT_B_write_enable, P2_q_b[9]_clock_1, , , );
P2_q_b[9]_clock_0 = GND;
P2_q_b[9]_clock_1 = GLOBAL(A1L5);
P2_q_b[9]_PORT_B_data_out = MEMORY(P2_q_b[9]_PORT_A_data_in_reg, P2_q_b[9]_PORT_B_data_in_reg, P2_q_b[9]_PORT_A_address_reg, P2_q_b[9]_PORT_B_address_reg, P2_q_b[9]_PORT_A_write_enable_reg, P2_q_b[9]_PORT_B_write_enable_reg, , , P2_q_b[9]_clock_0, P2_q_b[9]_clock_1, , , , );
P2_q_b[9] = P2_q_b[9]_PORT_B_data_out[0];

--P2_q_a[2] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[2] at M4K_X13_Y6
P2_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P2_q_a[9]_PORT_A_data_in_reg = DFFE(P2_q_a[9]_PORT_A_data_in, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_data_in = BUS(Q2_ram_rom_data_reg[9], Q2_ram_rom_data_reg[5], Q2_ram_rom_data_reg[3], Q2_ram_rom_data_reg[2]);
P2_q_a[9]_PORT_B_data_in_reg = DFFE(P2_q_a[9]_PORT_B_data_in, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[9]_PORT_A_address_reg = DFFE(P2_q_a[9]_PORT_A_address, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[9]_PORT_B_address_reg = DFFE(P2_q_a[9]_PORT_B_address, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_write_enable = GND;
P2_q_a[9]_PORT_A_write_enable_reg = DFFE(P2_q_a[9]_PORT_A_write_enable, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_write_enable = Q2L53;
P2_q_a[9]_PORT_B_write_enable_reg = DFFE(P2_q_a[9]_PORT_B_write_enable, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_clock_0 = GND;
P2_q_a[9]_clock_1 = GLOBAL(A1L5);
P2_q_a[9]_PORT_A_data_out = MEMORY(P2_q_a[9]_PORT_A_data_in_reg, P2_q_a[9]_PORT_B_data_in_reg, P2_q_a[9]_PORT_A_address_reg, P2_q_a[9]_PORT_B_address_reg, P2_q_a[9]_PORT_A_write_enable_reg, P2_q_a[9]_PORT_B_write_enable_reg, , , P2_q_a[9]_clock_0, P2_q_a[9]_clock_1, , , , );
P2_q_a[2] = P2_q_a[9]_PORT_A_data_out[3];

--P2_q_a[3] is SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[3] at M4K_X13_Y6
P2_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
P2_q_a[9]_PORT_A_data_in_reg = DFFE(P2_q_a[9]_PORT_A_data_in, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_data_in = BUS(Q2_ram_rom_data_reg[9], Q2_ram_rom_data_reg[5], Q2_ram_rom_data_reg[3], Q2_ram_rom_data_reg[2]);
P2_q_a[9]_PORT_B_data_in_reg = DFFE(P2_q_a[9]_PORT_B_data_in, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_address = BUS(~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
P2_q_a[9]_PORT_A_address_reg = DFFE(P2_q_a[9]_PORT_A_address, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_address = BUS(T2_safe_q[0], T2_safe_q[1], T2_safe_q[2], T2_safe_q[3], T2_safe_q[4], T2_safe_q[5], T2_safe_q[6], T2_safe_q[7], T2_safe_q[8], T2_safe_q[9]);
P2_q_a[9]_PORT_B_address_reg = DFFE(P2_q_a[9]_PORT_B_address, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_PORT_A_write_enable = GND;
P2_q_a[9]_PORT_A_write_enable_reg = DFFE(P2_q_a[9]_PORT_A_write_enable, P2_q_a[9]_clock_0, , , );
P2_q_a[9]_PORT_B_write_enable = Q2L53;
P2_q_a[9]_PORT_B_write_enable_reg = DFFE(P2_q_a[9]_PORT_B_write_enable, P2_q_a[9]_clock_1, , , );
P2_q_a[9]_clock_0 = GND;