mode.vhd

来自「这个是相当不错的EDA编程」· VHDL 代码 · 共 46 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MODE IS
    PORT (   clk: IN  STD_LOGIC;
             Set : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
             --Set1 : IN  STD_LOGIC;
             --Set2 : IN  STD_LOGIC;
             --Set3 : IN  STD_LOGIC;
             --Set4 : IN  STD_LOGIC;
             Fword : OUT integer range 0 to 255;
             cnt  :  out integer range 0 to 3    );
END MODE;
ARCHITECTURE behav OF MODE IS
    BEGIN
    signal set_mode:   STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal cs  :       STD_LOGIC;
    variable temp_fword: integer range 0 to 255;
	set_mode <= Set;
	temp_fword<=9;
	
	PROCESS(CLK)
	BEGIN
	if(set="1111")then
	   cs<='0';
	 else cs<='1';
	 end if;  
	 end process;
	
	PROCESS(cs)
	BEGIN
	if(cs'event and cs='1')then
	    if(temp_fword=255)then
	    temp_fword<=0;
	    cs<=cs+1;
	    else
	    temp_fword<=temp_fword+1;
	    end if;
	end if;
	end process;
	                 
	Fword<=temp_fword;
	
END behav;