dds_vhdl.fit.rpt

这个是相当不错的EDA编程

; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion -- Logic Duplication          ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error       ; On                       ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in F:/A_matiral/DDS_1k/dds_vhdl.fit.eqn.


+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/A_matiral/DDS_1k/dds_vhdl.pin.


+-----------------------------------------------------------+
; Fitter Resource Usage Summary                             ;
+--------------------------------+--------------------------+
; Resource                       ; Usage                    ;
+--------------------------------+--------------------------+
; Logic cells                    ; 734 / 2,910 ( 25 % )     ;
; Registers                      ; 600 / 3,210 ( 18 % )     ;
; Total LABs                     ; 117 / 291 ( 40 % )       ;
; Logic elements in carry chains ; 115                      ;
; User inserted logic cells      ; 0                        ;
; Virtual pins                   ; 0                        ;
; I/O pins                       ; 38 / 104 ( 36 % )        ;
;     -- Clock pins              ; 1 / 2 ( 50 % )           ;
; Global signals                 ; 8                        ;
; M4Ks                           ; 10 / 13 ( 76 % )         ;
; Total memory bits              ; 38,912 / 59,904 ( 64 % ) ;
; Total RAM block bits           ; 46,080 / 59,904 ( 76 % ) ;
; Global clocks                  ; 8 / 8 ( 100 % )          ;
; Maximum fan-out node           ; altera_internal_jtag~TDO ;
; Maximum fan-out                ; 397                      ;
; Total fan-out                  ; 3493                     ;
; Average fan-out                ; 4.43                     ;
+--------------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                     ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLK      ; 16    ; 1        ; 0            ; 8            ; 2           ; 231                   ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; FWORD[0] ; 58    ; 4        ; 18           ; 0            ; 1           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
; FWORD[1] ; 32    ; 1        ; 0            ; 3            ; 1           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;