dds_vhdl.map.summary

来自「这个是相当不错的EDA编程」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Sat Sep 10 08:44:39 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : DDS_VHDL
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Production
Total logic elements : 810
Total pins : 42
Total memory bits : 38,912
Total PLLs : 0