mode1.vhd

这个是相当不错的EDA编程

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MODE1 IS
    PORT (   clk: IN  STD_LOGIC;
             Pset : IN  STD_LOGIC;
             Setkey : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);             
             --Set1 : IN  STD_LOGIC;
             --Set2 : IN  STD_LOGIC;
             --Set3 : IN  STD_LOGIC;
             --Set4 : IN  STD_LOGIC;
             cnt  :  out integer range 0 to 3;  
             Fword : OUT integer range 0 to 255;
             Pword : OUT integer range 0 to 255
              );
END MODE1;

ARCHITECTURE behav OF MODE1 IS
    SIGNAL set_mode: STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL cs	: STD_LOGIC;

    
	
	--temp_fword<=9;
    BEGIN
    
    set_mode <= Setkey;
	--temp_fword := 9;
	
	PROCESS(CLK)
	
	BEGIN
	if(set_mode="1111")then
	   cs<='0';
	 else cs<='1';
	 end if;  
	 end process;
	
	PROCESS(cs)
	variable temp_fword: integer range 0 to 255:=9;
    variable temp_Pword: integer range 0 to 255:=0;
    variable temp_cnt: integer range 0 to 3:=0;
	BEGIN
	if( Pset='1' and cs='1')then
	    if(temp_fword=255)then
	        temp_fword:=0;
	        if(temp_cnt=1)then
	            temp_cnt:=0;
	         else 
	            temp_cnt:=temp_cnt+1;
	         end if;
	     else
	         temp_fword:=temp_fword+1;
	     end if;
	 elsif(Pset='0' and cs='1')then
	    temp_Pword:=temp_Pword+1;
	end if;
	
	Fword<=temp_fword;
	Pword<=temp_Pword;
	cnt<=temp_cnt;
	
	end process;
	                 	
END behav;