dds_all.map.rpt

这个是相当不错的EDA编程

; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                             ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                             ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------+
; ADDER10B.VHD                     ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/ADDER10B.VHD                              ;
; ADDER32B.VHD                     ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/ADDER32B.VHD                              ;
; DDS_ALL.bdf                      ; yes             ; User Block Diagram/Schematic File  ; E:/EDA/DDS_all/DDS_ALL.bdf                               ;
; REG10B.VHD                       ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/REG10B.VHD                                ;
; REG32B.VHD                       ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/REG32B.VHD                                ;
; SIN_ROM.VHD                      ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/SIN_ROM.VHD                               ;
; tt.vhd                           ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/tt.vhd                                    ;
; MODE1.vhd                        ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/MODE1.vhd                                 ;
; word.vhd                         ; yes             ; User VHDL File                     ; E:/EDA/DDS_all/word.vhd                                  ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; d:/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/lpm_decode.inc        ;
; aglobal60.inc                    ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/aglobal60.inc         ;
; altsyncram.inc                   ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                    ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_sq71.tdf           ; yes             ; Auto-Generated Megafunction        ; E:/EDA/DDS_all/db/altsyncram_sq71.tdf                    ;
; db/altsyncram_kol2.tdf           ; yes             ; Auto-Generated Megafunction        ; E:/EDA/DDS_all/db/altsyncram_kol2.tdf                    ;
; sld_mod_ram_rom.vhd              ; yes             ; Encrypted Megafunction             ; d:/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd   ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction             ; d:/quartus/libraries/megafunctions/sld_rom_sr.vhd        ;
; altpll.tdf                       ; yes             ; Megafunction                       ; d:/quartus/libraries/megafunctions/altpll.tdf            ;
; stratix_pll.inc                  ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/stratix_pll.inc       ;
; stratixii_pll.inc                ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/stratixii_pll.inc     ;
; cycloneii_pll.inc                ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/cycloneii_pll.inc     ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction             ; d:/quartus/libraries/megafunctions/sld_hub.vhd           ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                       ; d:/quartus/libraries/megafunctions/lpm_shiftreg.tdf      ;
; lpm_constant.inc                 ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/lpm_constant.inc      ;
; dffeea.inc                       ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/dffeea.inc            ;
; lpm_decode.tdf                   ; yes             ; Megafunction                       ; d:/quartus/libraries/megafunctions/lpm_decode.tdf        ;
; declut.inc                       ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/declut.inc            ;
; altshift.inc                     ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/altshift.inc          ;
; lpm_compare.inc                  ; yes             ; Other                              ; d:/quartus/libraries/megafunctions/lpm_compare.inc       ;
; db/decode_ogi.tdf                ; yes             ; Auto-Generated Megafunction        ; E:/EDA/DDS_all/db/decode_ogi.tdf                         ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction             ; d:/quartus/libraries/megafunctions/sld_dffex.vhd         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 266                      ;
;     -- Combinational with no register       ; 106                      ;
;     -- Register only                        ; 28                       ;
;     -- Combinational with a register        ; 132                      ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 94                       ;
;     -- 3 input functions                    ; 66                       ;
;     -- 2 input functions                    ; 73                       ;
;     -- 1 input functions                    ; 3                        ;
;     -- 0 input functions                    ; 2                        ;
;         -- Combinational cells for routing  ; 0                        ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 230                      ;
;     -- arithmetic mode                      ; 36                       ;
;     -- qfbk mode                            ; 0                        ;
;     -- register cascade mode                ; 0                        ;
;     -- synchronous clear/load mode          ; 59                       ;
;     -- asynchronous clear/load mode         ; 90                       ;
;                                             ;                          ;
; Total registers                             ; 160                      ;
; Total logic cells in carry chains           ; 43                       ;
; I/O pins                                    ; 30                       ;
; Total memory bits                           ; 20480                    ;
; Total PLLs                                  ; 1                        ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO ;
; Maximum fan-out                             ; 185                      ;
; Total fan-out                               ; 1469                     ;
; Average fan-out                             ; 4.62                     ;
+---------------------------------------------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                   ;