dds_vhdl.map.rpt

这个是相当不错的EDA编程

+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 17    ;
; Number of registers using Synchronous Load   ; 32    ;
; Number of registers using Asynchronous Clear ; 382   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 316   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                             ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; 0              ; auto_signaltap_0 ; 36                  ; 36               ; 512          ; 1              ; 0                       ; yes             ; no               ; 0                          ; 0                       ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting                                                                                                        ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                                 ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------------------+
; 0              ; rom         ; 10    ; 1024  ; Read/Write ; |DDS_VHDL|SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated ;
; 1              ; rom         ; 10    ; 1024  ; Read/Write ; |DDS_VHDL|SIN_ROM:u6|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------------------+


+-----------+
; Hierarchy ;
+-----------+
DDS_VHDL
 |-- sld_signaltap:auto_signaltap_0
      |-- sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst
           |-- lpm_counter:\adv_point_3_and_more:advance_pointer_counter
                |-- cntr_hv7:auto_generated
           |-- lpm_shiftreg:info_data_shift_out
           |-- lpm_shiftreg:ram_data_shift_out
           |-- lpm_counter:read_pointer_counter
                |-- cntr_mk7:auto_generated
      |-- altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram
           |-- altsyncram_5m82:auto_generated
      |-- sld_rom_sr:crc_rom_sr
      |-- sld_ela_control:ela_control
           |-- sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm
                |-- sld_mbpmg:\trigger_modules_gen:0:trigger_match
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1
                     |-- sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1