fifoctlr_cc.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fifoctlr_cc IS
   PORT (clock_in:        	IN  STD_LOGIC;
         read_enable_in:  		IN  STD_LOGIC;
         write_enable_in: 		IN  STD_LOGIC;
         write_data_in:   		IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
         fifo_gsr_in:     		IN  STD_LOGIC;
         read_data_out:   		OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         full_out:        		OUT STD_LOGIC;
         empty_out:       	OUT STD_LOGIC;
         fifocount_out:   		OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END fifoctlr_cc;
ARCHITECTURE fifoctlr_cc_hdl OF fifoctlr_cc IS
   SIGNAL clock:               STD_LOGIC;
   SIGNAL read_enable:          STD_LOGIC;
   SIGNAL write_enable:         STD_LOGIC;
   SIGNAL fifo_gsr:             STD_LOGIC;
   SIGNAL read_data:           STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
   SIGNAL write_data:          STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL full:                STD_LOGIC;
   SIGNAL empty:              STD_LOGIC;
   SIGNAL read_addr:           STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
   SIGNAL write_addr:          STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
   SIGNAL fcounter:            STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
   SIGNAL read_allow:          STD_LOGIC;
   SIGNAL write_allow:         STD_LOGIC;
   SIGNAL fcnt_allow:          STD_LOGIC;
   SIGNAL fcntandout:          STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL ra_or_fcnt0:         STD_LOGIC;
   SIGNAL wa_or_fcnt0:        STD_LOGIC;
   SIGNAL emptyg:             STD_LOGIC;
   SIGNAL fullg:              STD_LOGIC;
   SIGNAL gnd_bus:           STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL gnd:                STD_LOGIC;
   SIGNAL pwr:               STD_LOGIC;
component BUFGP
   port (
      I: IN std_logic;  
      O: OUT std_logic);
END component;

component RAMB4_S8_S8
   port (
      ADDRA: IN std_logic_vector(8 downto 0);
      ADDRB: IN std_logic_vector(8 downto 0);
      DIA:   IN std_logic_vector(7 downto 0);
      DIB:   IN std_logic_vector(7 downto 0);
      WEA:   IN std_logic;
      WEB:   IN std_logic;
      CLKA:  IN std_logic;
      CLKB:  IN std_logic;
      RSTA:  IN std_logic;
      RSTB:  IN std_logic;
      ENA:   IN std_logic;
      ENB:   IN std_logic;
      DOA:   OUT std_logic_vector(7 downto 0);
      DOB:   OUT std_logic_vector(7 downto 0));
END component;

BEGIN
   read_enable <= read_enable_in;
   write_enable <= write_enable_in;
   fifo_gsr <= fifo_gsr_in;
   write_data <= write_data_in;
   read_data_out <= read_data;
   full_out <= full;
   empty_out <= empty;
   gnd_bus <= "00000000";
   gnd <= '0';
   pwr <= '1';
   
-- 全局BUFFER用来去抖       
--------------------------------------------------------------------------
 
gclk1: BUFGP Port Map (I => clock_in, O => clock);

--------------------------------------------------------------------------
--                                                                      --
-- 块RAM采用IP核511x8, of which one     -- 
-- address location is sacrificed for the overall speed of the design.  --
--------------------------------------------------------------------------

bram1: RAMB4_S8_S8 port map (ADDRA => read_addr, ADDRB => write_addr,
              DIA => gnd_bus, DIB => write_data, WEA => gnd, WEB => pwr,
              CLKA => clock, CLKB => clock, RSTA => gnd, RSTB => gnd, 
              ENA => read_allow, ENB => write_allow, DOA => read_data );

---------------------------------------------------------------
--设置使能标志，控制时钟使能来读写和计数操作
---------------------------------------------------------------
 
proc1: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      read_allow <= '0';
   ELSIF (clock'EVENT AND clock = '1') THEN
      read_allow <= read_enable AND NOT (fcntandout(0) AND fcntandout(1)
                    AND NOT write_allow);
   END IF;
END PROCESS proc1;

proc2: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      write_allow <= '0';
   ELSIF (clock'EVENT AND clock = '1') THEN
      write_allow <= write_enable AND NOT (fcntandout(2) AND fcntandout(3)
                     AND NOT read_allow);
   END IF;
END PROCESS proc2;

fcnt_allow <= write_allow XOR read_allow;

---------------------------------------------------------------
--   空标志初始化，下一个周期写使能有效当FIFO计数器大于1时读有效使能
   ---------------------------------------------------------------

ra_or_fcnt0 <= (read_allow OR NOT fcounter(0));
fcntandout(0) <= NOT (fcounter(4) OR fcounter(3) OR fcounter(2) OR fcounter(1));
fcntandout(1) <= NOT (fcounter(8) OR fcounter(7) OR fcounter(6) OR fcounter(5));
emptyg <= (fcntandout(0) AND fcntandout(1) AND ra_or_fcnt0 AND NOT write_allow);

proc3: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      empty <= '1';
   ELSIF (clock'EVENT AND clock = '1') THEN
      empty <= emptyg;
   END IF;
END PROCESS proc3;
wa_or_fcnt0 <= (write_allow OR fcounter(0));
fcntandout(2) <= (fcounter(4) AND fcounter(3) AND fcounter(2) AND fcounter(1));
fcntandout(3) <= (fcounter(8) AND fcounter(7) AND fcounter(6) AND fcounter(5));
fullg <= (fcntandout(2) AND fcntandout(3) AND wa_or_fcnt0 AND NOT read_allow);

proc4: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      full <= '1';
   ELSIF (clock'EVENT AND clock = '1') THEN
      full <= fullg;
   END IF;
END PROCESS proc4;

----------------------------------------------------------------
--产生读写地址指针，使用二进制计数器，仿真简便
----------------------------------------------------------------

proc5: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      read_addr <= "000000000";
   ELSIF (clock'EVENT AND clock = '1') THEN
      IF (read_allow = '1') THEN
         read_addr <= read_addr + '1';
      END IF;
   END IF;
END PROCESS proc5;

proc6: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      write_addr <= "000000000";
   ELSIF (clock'EVENT AND clock = '1') THEN
      IF (write_allow = '1') THEN
         write_addr <= write_addr + '1';
      END IF;
   END IF;
END PROCESS proc6;

----------------------------------------------------------------
-- 生成FIFO计数器输出，用以判定FIFO是否为满，并生成空和满的标志位
----------------------------------------------------------------

proc7: PROCESS (clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      fcounter <= "000000000";
   ELSIF (clock'EVENT AND clock = '1') THEN
      IF (fcnt_allow = '1') THEN
         IF (read_allow = '0') THEN
            fcounter <= fcounter + '1';
         ELSE
            fcounter <= fcounter - '1';
         END IF;
      END IF;
   END IF;
END PROCESS proc7;
fifocount_out <= fcounter(8 downto 5);

END fifoctlr_cc_hdl;