fifoasyn.vhd

VHDL的例子

   IF (fifo_gsr = '1') THEN
      read_addrgray <= "100000001";
   ELSIF (read_clock'EVENT AND read_clock = '1') THEN
      IF (read_allow = '1') THEN
         read_addrgray <= read_nextgray;
      END IF;
   END IF;
END PROCESS proc5;
 
proc6: PROCESS (read_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      read_lastgray <= "100000011";
   ELSIF (read_clock'EVENT AND read_clock = '1') THEN
      IF (read_allow = '1') THEN
         read_lastgray <= read_addrgray;
      END IF;
   END IF;
END PROCESS proc6;
 
----------------------------------------------------------------
--  产生写地址指针，和上面相同                                --
----------------------------------------------------------------

proc7: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      write_addr <= "000000000";
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      IF (write_allow = '1') THEN
         write_addr <= write_addr + 1;
      END IF;
   END IF;
END PROCESS proc7;
 
proc8: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      write_nextgray <= "100000000";
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      IF (write_allow = '1') THEN
         write_nextgray(8) <= write_addr(8);
         write_nextgray(7) <= write_addr(8) XOR write_addr(7);
         write_nextgray(6) <= write_addr(7) XOR write_addr(6);
         write_nextgray(5) <= write_addr(6) XOR write_addr(5);
         write_nextgray(4) <= write_addr(5) XOR write_addr(4);
         write_nextgray(3) <= write_addr(4) XOR write_addr(3);
         write_nextgray(2) <= write_addr(3) XOR write_addr(2);
         write_nextgray(1) <= write_addr(2) XOR write_addr(1);
         write_nextgray(0) <= write_addr(1) XOR write_addr(0);
      END IF;
   END IF;
END PROCESS proc8;
 
proc9: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      write_addrgray <= "100000001";
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      IF (write_allow = '1') THEN
         write_addrgray <= write_nextgray;
      END IF;
   END IF;
END PROCESS proc9;

----------------------------------------------------------------
-- 改变的FOFO输出状态。
--  用来判断FIFO的数据充满程度，算法是依据读写指针的距离 --
----------------------------------------------------------------

proc10: PROCESS (read_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      read_truegray <= "000000000";
   ELSIF (read_clock'EVENT AND read_clock = '1') THEN
      read_truegray(8) <= read_addr(8);
      read_truegray(7) <= read_addr(8) XOR read_addr(7);
      read_truegray(6) <= read_addr(7) XOR read_addr(6);
      read_truegray(5) <= read_addr(6) XOR read_addr(5);
      read_truegray(4) <= read_addr(5) XOR read_addr(4);
      read_truegray(3) <= read_addr(4) XOR read_addr(3);
      read_truegray(2) <= read_addr(3) XOR read_addr(2);
      read_truegray(1) <= read_addr(2) XOR read_addr(1);
      read_truegray(0) <= read_addr(1) XOR read_addr(0);
   END IF;
END PROCESS proc10;
 
proc11: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      rag_writesync <= "000000000";
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      rag_writesync <= read_truegray;
   END IF;
END PROCESS proc11;
 
xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR 
              rag_writesync(5));
xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR 
              rag_writesync(1));

ra_writesync(8) <= rag_writesync(8);
ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7));
ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6));
ra_writesync(5) <= xorout(0);
ra_writesync(4) <= (xorout(0) XOR rag_writesync(4));
ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3));
ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)
                              XOR rag_writesync(2));
ra_writesync(1) <= (xorout(0) XOR xorout(1));
ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0));

proc11: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      write_addrr <= "000000000";
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      write_addrr <= write_addr;
   END IF;
END PROCESS proc11;
 
proc13: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      fifostatus <= "000000000";
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      IF (full = '0') THEN
         fifostatus <= (write_addrr - ra_writesync);
      END IF;
   END IF;
END PROCESS proc13;


ecomp(0) <= (NOT (write_addrgray(0) XOR read_addrgray(0)) AND empty) OR
            (NOT (write_addrgray(0) XOR read_nextgray(0)) AND NOT empty);
ecomp(1) <= (NOT (write_addrgray(1) XOR read_addrgray(1)) AND empty) OR
            (NOT (write_addrgray(1) XOR read_nextgray(1)) AND NOT empty);
ecomp(2) <= (NOT (write_addrgray(2) XOR read_addrgray(2)) AND empty) OR
            (NOT (write_addrgray(2) XOR read_nextgray(2)) AND NOT empty);
ecomp(3) <= (NOT (write_addrgray(3) XOR read_addrgray(3)) AND empty) OR
            (NOT (write_addrgray(3) XOR read_nextgray(3)) AND NOT empty);
ecomp(4) <= (NOT (write_addrgray(4) XOR read_addrgray(4)) AND empty) OR
            (NOT (write_addrgray(4) XOR read_nextgray(4)) AND NOT empty);
ecomp(5) <= (NOT (write_addrgray(5) XOR read_addrgray(5)) AND empty) OR
            (NOT (write_addrgray(5) XOR read_nextgray(5)) AND NOT empty);
ecomp(6) <= (NOT (write_addrgray(6) XOR read_addrgray(6)) AND empty) OR
            (NOT (write_addrgray(6) XOR read_nextgray(6)) AND NOT empty);
ecomp(7) <= (NOT (write_addrgray(7) XOR read_addrgray(7)) AND empty) OR
            (NOT (write_addrgray(7) XOR read_nextgray(7)) AND NOT empty);
ecomp(8) <= (NOT (write_addrgray(8) XOR read_addrgray(8)) AND empty) OR
            (NOT (write_addrgray(8) XOR read_nextgray(8)) AND NOT empty);

emuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr,       S=>ecomp(0),LO=>emuxcyo(0));
emuxcy1: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(0),S=>ecomp(1),LO=>emuxcyo(1));
emuxcy2: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(1),S=>ecomp(2),LO=>emuxcyo(2));
emuxcy3: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(2),S=>ecomp(3),LO=>emuxcyo(3));
emuxcy4: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(3),S=>ecomp(4),LO=>emuxcyo(4));
emuxcy5: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(4),S=>ecomp(5),LO=>emuxcyo(5));
emuxcy6: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(5),S=>ecomp(6),LO=>emuxcyo(6));
emuxcy7: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(6),S=>ecomp(7),LO=>emuxcyo(7));
emuxcy8: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(7),S=>ecomp(8),LO=>emptyg);

fcomp(0) <= (NOT (read_lastgray(0) XOR write_addrgray(0)) AND full) OR
            (NOT (read_lastgray(0) XOR write_nextgray(0)) AND NOT full);
fcomp(1) <= (NOT (read_lastgray(1) XOR write_addrgray(1)) AND full) OR
            (NOT (read_lastgray(1) XOR write_nextgray(1)) AND NOT full);
fcomp(2) <= (NOT (read_lastgray(2) XOR write_addrgray(2)) AND full) OR
            (NOT (read_lastgray(2) XOR write_nextgray(2)) AND NOT full);
fcomp(3) <= (NOT (read_lastgray(3) XOR write_addrgray(3)) AND full) OR
            (NOT (read_lastgray(3) XOR write_nextgray(3)) AND NOT full);
fcomp(4) <= (NOT (read_lastgray(4) XOR write_addrgray(4)) AND full) OR
            (NOT (read_lastgray(4) XOR write_nextgray(4)) AND NOT full);
fcomp(5) <= (NOT (read_lastgray(5) XOR write_addrgray(5)) AND full) OR
            (NOT (read_lastgray(5) XOR write_nextgray(5)) AND NOT full);
fcomp(6) <= (NOT (read_lastgray(6) XOR write_addrgray(6)) AND full) OR
            (NOT (read_lastgray(6) XOR write_nextgray(6)) AND NOT full);
fcomp(7) <= (NOT (read_lastgray(7) XOR write_addrgray(7)) AND full) OR
            (NOT (read_lastgray(7) XOR write_nextgray(7)) AND NOT full);
fcomp(8) <= (NOT (read_lastgray(8) XOR write_addrgray(8)) AND full) OR
            (NOT (read_lastgray(8) XOR write_nextgray(8)) AND NOT full);

fmuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr,      S=>fcomp(0),LO=>fmuxcyo(0));
fmuxcy1: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(0),S=>fcomp(1),LO=>fmuxcyo(1));
fmuxcy2: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(1),S=>fcomp(2),LO=>fmuxcyo(2));
fmuxcy3: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(2),S=>fcomp(3),LO=>fmuxcyo(3));
fmuxcy4: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(3),S=>fcomp(4),LO=>fmuxcyo(4));
fmuxcy5: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(4),S=>fcomp(5),LO=>fmuxcyo(5));
fmuxcy6: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(5),S=>fcomp(6),LO=>fmuxcyo(6));
fmuxcy7: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(6),S=>fcomp(7),LO=>fmuxcyo(7));
fmuxcy8: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(7),S=>fcomp(8),LO=>fullg);
END fifoctlr_ic_hdl;