fifoasyn.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fifoasyn IS
   PORT (
read_clock_in:   	IN  STD_LOGIC;
write_clock_in:   	IN  STD_LOGIC;
read_enable_in:   	IN  STD_LOGIC;
         	write_enable_in:  	IN  STD_LOGIC;
         	fifo_gsr_in:      	IN  STD_LOGIC;
         	write_data_in:    	IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
         	read_data_out:    	OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         	full_out:         	OUT STD_LOGIC;
         	empty_out:       	OUT STD_LOGIC;
         	fifostatus_out:  	OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END fifoasyn;

ARCHITECTURE fifoctlr_ic_hdl OF fifoasyn IS
   SIGNAL read_clock:            	STD_LOGIC;
   SIGNAL write_clock:           	STD_LOGIC;
   SIGNAL read_enable:           	STD_LOGIC;
   SIGNAL write_enable:          	STD_LOGIC;
   SIGNAL fifo_gsr:              	STD_LOGIC;
   SIGNAL read_data:            	STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL write_data:            	STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL full:                  	STD_LOGIC;
   SIGNAL empty:                STD_LOGIC;
   SIGNAL read_addr:             STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL read_addrgray:         	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL read_nextgray:         	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL read_lastgray:          	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL write_addr:            	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL write_addrgray:         STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL write_nextgray:         STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL fifostatus:             	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL read_allow:           	STD_LOGIC;
   SIGNAL write_allow:           	STD_LOGIC;
   SIGNAL empty_allow:          	STD_LOGIC;
   SIGNAL full_allow:            	STD_LOGIC;
   SIGNAL ecomp:               	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL fcomp:                STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL emuxcyo:              STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL fmuxcyo:              STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL emptyg:               STD_LOGIC;
   SIGNAL fullg:                 STD_LOGIC;
   SIGNAL read_truegray:         	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL rag_writesync:         	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL ra_writesync:          	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL write_addrr:           	STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL xorout:               	STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL gnd_bus:              STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL gnd:                  STD_LOGIC;
   SIGNAL pwr:                  STD_LOGIC;
 COMPONENT BUFGP
   port (
      I: IN std_logic;
      O: OUT std_logic);
END COMPONENT;
 
COMPONENT MUXCY_L
   port (
      DI:  IN std_logic;
      CI:  IN std_logic;
      S:   IN std_logic;
      LO: OUT std_logic);
END COMPONENT;
 
COMPONENT RAMB4_S8_S8
   port (
      ADDRA: IN std_logic_vector(8 downto 0);
      ADDRB: IN std_logic_vector(8 downto 0);
      DIA:   IN std_logic_vector(7 downto 0);
      DIB:   IN std_logic_vector(7 downto 0);
      WEA:   IN std_logic;
      WEB:   IN std_logic;
      CLKA:  IN std_logic;
      CLKB:  IN std_logic;
      RSTA:  IN std_logic;
      RSTB:  IN std_logic;
      ENA:   IN std_logic;
      ENB:   IN std_logic;
      DOA:   OUT std_logic_vector(7 downto 0);
      DOB:   OUT std_logic_vector(7 downto 0));
END COMPONENT;
 
BEGIN
   read_enable <= read_enable_in;
   write_enable <= write_enable_in;
   fifo_gsr <= fifo_gsr_in;
   write_data <= write_data_in;
   read_data_out <= read_data;
   full_out <= full;
   empty_out <= empty;
   fifostatus_out <= fifostatus(8 downto 5);
   gnd_bus <= "00000000";
   gnd <= '0';
   pwr <= '1';

--------------------------------------------------------------------------                                   
-- 全局的输入时钟缓冲器用来去除抖动
--------------------------------------------------------------------------

gclk1: BUFGP port map (I => read_clock_in, O => read_clock);
gclk2: BUFGP port map (I => write_clock_in, O => write_clock);

--------------------------------------------------------------------------
--   块RAM模块511x8
--------------------------------------------------------------------------

bram1: RAMB4_S8_S8 port map (ADDRA => read_addr, ADDRB => write_addr,
              DIA => gnd_bus, DIB => write_data, WEA => gnd, WEB => pwr, 
              CLKA => read_clock, CLKB => write_clock, RSTA => gnd, 
              RSTB => gnd, ENA => read_allow, ENB => write_allow, 
              DOA => read_data );
 
----------------------------------------------------------------
-- 读写控制                            --
----------------------------------------------------------------

read_allow <= (read_enable AND NOT empty);
write_allow <= (write_enable AND NOT full);

full_allow <= (full OR write_enable);
empty_allow <= (empty OR read_enable);
 
---------------------------------------------------------------
--  初始化产生空标志位，格雷码计数器相等时产生空标志位，当FIFO里有一个字，将要读出时产生空标志位。                                                      --
---------------------------------------------------------------

proc1: PROCESS (read_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      empty <= '1';
   ELSIF (read_clock'EVENT AND read_clock = '1') THEN
      IF (empty_allow = '1') THEN
         empty <= emptyg;
      END IF;
   END IF;
END PROCESS proc1;
 
---------------------------------------------------------------
-- 上电初始化清除满标志，当写格雷码计数器的下一个地址等于读地址的计数器，产生满标志。
---------------------------------------------------------------

proc2: PROCESS (write_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      full <= '1';
   ELSIF (write_clock'EVENT AND write_clock = '1') THEN
      IF (full_allow = '1') THEN
         full <= fullg;
      END IF;
   END IF;
END PROCESS proc2;
 
----------------------------------------------------------------
-- 产生读地址指针，最初时二进制的读地址，然后通过二进制到格雷码的转换，转为格雷码。
格雷码地址适于在异步状态下使用。                             --
----------------------------------------------------------------

proc3: PROCESS (read_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      read_addr <= "000000000";
   ELSIF (read_clock'EVENT AND read_clock = '1') THEN
      IF (read_allow = '1') THEN
         read_addr <= read_addr + 1;
      END IF;
   END IF;
END PROCESS proc3;
 
proc4: PROCESS (read_clock, fifo_gsr)
BEGIN
   IF (fifo_gsr = '1') THEN
      read_nextgray <= "100000000";
   ELSIF (read_clock'EVENT AND read_clock = '1') THEN
      IF (read_allow = '1') THEN
         read_nextgray(8) <= read_addr(8);
         read_nextgray(7) <= read_addr(8) XOR read_addr(7);
         read_nextgray(6) <= read_addr(7) XOR read_addr(6);
         read_nextgray(5) <= read_addr(6) XOR read_addr(5);
         read_nextgray(4) <= read_addr(5) XOR read_addr(4);
         read_nextgray(3) <= read_addr(4) XOR read_addr(3);
         read_nextgray(2) <= read_addr(3) XOR read_addr(2);
         read_nextgray(1) <= read_addr(2) XOR read_addr(1);
         read_nextgray(0) <= read_addr(1) XOR read_addr(0);
      END IF;
   END IF;
END PROCESS proc4;
 
proc5: PROCESS (read_clock, fifo_gsr)
BEGIN