pipelined_stages_p.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PIPELINED_STAGES_P IS
	GENERIC(DATA_BITS	: INTEGER := 36);
	PORT(
	     ui_read_data	: OUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     write_data  	: OUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     rw_tff		: OUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     read_data	: IN  STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     ui_write_data	: IN  STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     ui_rw_n		: IN  STD_LOGIC;
	     fpga_clk		: IN  STD_LOGIC);
END PIPELINED_STAGES_P;

ARCHITECTURE RTL OF PIPELINED_STAGES_P IS
SIGNAL rw_p1		: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL l rw_p2		: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rw_p3		: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL write_data_p	: STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);

BEGIN

	PROCESS (fpga_clk)
	BEGIN
		IF (fpga_clk 'EVENT AND fpga_clk = '1') THEN
			FOR i IN 0 TO 3 LOOP
				rw_p1(i)   <= ui_rw_n;
				rw_p2(i)   <= rw_p1(i);
				rw_p3(i)   <= rw_p2(i);
				rw_tff(i)   <= rw_p1(i);
				rw_tff(i+4) <= rw_p1(i);
				rw_tff(i+8) <= rw_p1(i);
				rw_tff(i+11)<= rw_p1(i);
				rw_tff(i+16)<= rw_p1(i);
				rw_tff(i+20)<= rw_p1(i);
				rw_tff(i+24)<= rw_p1(i);
				rw_tff(i+28)<= rw_p1(i);
				rw_tff(i+32)<= rw_p1(i);
			END LOOP;
	
			FOR i IN 0 TO DATA_BITS-1 LOOP
				write_data_p(i) <= ui_write_data(i);
				write_data(i)  <= write_data_p(i);
			END LOOP;
			
			IF (rw_p3(0) = '1') THEN 
				FOR i IN 0 TO 8 LOOP
					ui_read_data(i) <= read_data(i);
				END LOOP;
			END IF;
			IF (rw_p3(1) = '1') THEN 
				FOR i IN 9 TO 17 LOOP
					ui_read_data(i) <= read_data(i);
				END LOOP;
			END IF;
			IF (rw_p3(2) = '1') THEN 
				FOR i IN 18 TO 26 LOOP
					ui_read_data(i) <= read_data(i);
				END LOOP;
			END IF;
			IF (rw_p3(3) = '1') THEN 
				FOR i IN 27 TO 35 LOOP
					ui_read_data(i) <= read_data(i);
				END LOOP;
			END IF;
								
		END IF;
	END PROCESS;
END RTL;