addrbits_out.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;

ENTITY ADDRBITS_OUT IS
	GENERIC (ADDR_BITS :INTEGER :=16);
	PORT(
-- 和测试器接口
	     ui_addr : IN  STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);
	     fpga_clk: IN  STD_LOGIC;
-- 和ZBT SRAM的地址接口
	     addr    : OUT STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0));
end ADDRBITS_OUT;

ARCHITECTURE RTL OF ADDRBITS_OUT IS
SIGNAL addr_p : STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);

COMPONENT OBUF_F_16
	PORT( I : IN  STD_LOGIC;
	      O : OUT STD_LOGIC);
END COMPONENT;

BEGIN

	PROCESS(fpga_clk) 
BEGIN
		IF (fpga_clk 'EVENT AND fpga_clk = '1') THEN
			FOR i IN 0 TO ADDR_BITS-1 LOOP
				addr_p(i) <= ui_addr(i);
			END LOOP;
		END IF;
	END PROCESS;

g0:	FOR i IN 0 TO ADDR_BITS-1 GENERATE

	obuf_addr: OBUF_F_16 PORT MAP(
I=>addr_p(i), O=>addr(i));

	END GENERATE;
	
END RTL;