pipelined.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE my_ctlr_p IS
	COMPONENT CTLR_P
	GENERIC(ADDR_BITS  	: INTEGER := 16;
		     DATA_BITS  	: INTEGER := 36);
	PORT(
	     dq		  : INOUT   std_logic_vector(DATA_BITS-1 DOWNTO 0);
	     addr	  : OUT    std_logic_vector(ADDR_BITS-1 DOWNTO 0);
	     lbo_n	  : OUT    STD_LOGIC;
	     clk	      : OUT    STD_LOGIC;
	     cke_n	  : OUT    STD_LOGIC;
	     ld_n	  : OUT    STD_LOGIC;
	     bwa_n	  : OUT    STD_LOGIC;
	     bwb_n	  : OUT    STD_LOGIC;
	     bwc_n	  : OUT    STD_LOGIC;
	     bwd_n	  : OUT    STD_LOGIC;
	     rw_n	  : OUT    STD_LOGIC;
	     oe_n	  : OUT    STD_LOGIC;
	     ce_n	  : OUT    STD_LOGIC;
	     ce2	      : OUT    STD_LOGIC;
	     ce2_n	  : OUT    STD_LOGIC;
	     zz		  : OUT    STD_LOGIC;
	     fpga_clk	  : OUT    STD_LOGIC;
	     ui_addr	  : IN     STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);
	     ui_write_data : IN	   STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     ui_rw_n	    : IN     STD_LOGIC;
	     ui_rw_n_ctlr : IN     STD_LOGIC;
	     ui_board_clk : IN     STD_LOGIC;
	     ui_read_data : OUT    STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     ui_clk_mirror_locked_int : OUT    STD_LOGIC;
	     ui_clk_mirror_locked_ext : OUT    STD_LOGIC;
	     ui_clk_mirror_fb        IN     STD_LOGIC);
	END COMPONENT;
END my_ctlr_p;

LIBRARY IEEE;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CTLR_P IS
	GENERIC (ADDR_BITS : integer := 16;
		     DATA_BITS : integer := 36);
	PORT(
	     dq	    : INOUT  STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);--对RAM双向数据总线
	     addr	: OUT    STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);--向RAM输出地址
	     lbo_n	: OUT    STD_LOGIC;  --突发模式(0 = Linear, 1 = Interleaved)
	     clk	    : OUT    STD_LOGIC;  --送到RAM的2倍时钟
	     cke_n    :OUT    STD_LOGIC;  --同步时钟使能
	     ld_n	  :OUT    STD_LOGIC;  --Synchronous address Adv/LD
	     bwa_n	  : OUT    STD_LOGIC;  --同步Byte写使能A
	     bwb_n	  : OUT    STD_LOGIC;  --同步Byte写使能B
	     bwc_n	  : OUT    STD_LOGIC;  --同步Byte写使能C
	     bwd_n	  : OUT    STD_LOGIC;  --同步Byte写使能D
	     rw_n	  : OUT    STD_LOGIC;  --对RAM读写控制
	     oe_n	  : OUT    STD_LOGIC;  --输出使能
	     ce_n	  : OUT    STD_LOGIC;  --同步片选
	     ce2	      : OUT    STD_LOGIC;  --同步芯片使能
	     ce2_n	  : OUT    STD_LOGIC;  --同步芯片使能
	     zz		  : OUT    STD_LOGIC;  --Snooze Mode
	     fpga_clk	  : OUT    STD_LOGIC;  --内部使用的时钟(= ui_board_clk * 2)

	     ui_addr	  : IN     STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);--用户输入地址
	     ui_write_data: IN     STD_LOGIC_VECTOR (DATA_BITS-1 DOWNTO 0);--用户输入数据
	     ui_rw_n	    : IN     STD_LOGIC;  --用户读写控制
	     ui_rw_n_ctlr : IN     STD_LOGIC;  --用户读写控制
	     ui_board_clk : IN     STD_LOGIC;  --外部输入时钟
	     ui_read_data : OUT    STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);--从SRAM中读取的数据
	     ui_clk_mirror_locked_int : OUT    STD_LOGIC;
	     ui_clk_mirror_locked_ext : OUT    STD_LOGIC;
	     ui_clk_mirror_fb       :IN     STD_LOGIC); --反馈时钟
END CTLR_P;

ARCHITECTURE RTL OF CTLR_P IS
SIGNAL write_data	: STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
SIGNAL read_data		: STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
SIGNAL rw_tff		: STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
SIGNAL rw_n_p		: STD_LOGIC;
SIGNAL fpga_clk_a	: STD_LOGIC;

COMPONENT DATABITS_INOUT
	PORT(
	     read_data 	: OUT   STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     dq			: INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     write_data	: IN    STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     rw_tff		: IN    STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     fpga_clk		: IN    STD_LOGIC);
END COMPONENT;
 
COMPONENT PIPELINED_STAGES_P 
	PORT(
	     ui_read_data	: OUT   STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     write_data	: OUT   STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     rw_tff		: OUT   STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     ui_write_data : IN    STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
 	     ui_rw_n		: IN    STD_LOGIC;
	     read_data	: IN    STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     fpga_clk		: IN    STD_LOGIC);
END COMPONENT;

COMPONENT ADDRBITS_OUT
	PORT(
	     addr	: OUT STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);
	     ui_addr	: IN  STD_LOGIC_VECTOR(ADDR_BITS-1 DOWNTO 0);
	     fpga_clk	: IN  STD_LOGIC);
END COMPONENT;

COMPONENT OBUF_F_16
	PORT(I : IN STD_LOGIC; O : OUT STD_LOGIC);
END COMPONENT;

COMPONENT TIE_UNUSED_SIGS
	PORT(
	     lbo_n, cke_n, ld_n		: OUT STD_LOGIC;
	     bwa_n, bwb_n, bwc_n	: OUT STD_LOGIC;
	     bwd_n, oe_n, ce_n		: OUT STD_LOGIC;
	     ce2, ce2_n, zz		: OUT STD_LOGIC);
END COMPONENT; 

COMPONENT DLL_2X_BOARD
	PORT(
	     clk2x_int				: OUT STD_LOGIC;
	     ui_clk_mirror_locked_int	: OUT STD_LOGIC;
	     clk2x_ext				: OUT STD_LOGIC;
	     ui_clk_mirror_locked_ext	: OUT STD_LOGIC;
	     ui_board_clk			: IN    STD_LOGIC;
	     ui_clk_mirror_fb		: IN    STD_LOGIC);
END COMPONENT;
BEGIN
---------------------------------------------------------------------------------------
-- 对管线ZBT SRAM而言，写数据和读/要经过两级处理，对涌流模式需要一级处理就够了 
---------------------------------------------------------------------------------------

I_pipelined_stages_p: PIPELINED_STAGES_P  PORT MAP(
	     				  ui_read_data=>ui_read_data,
	     				  write_data=>write_data,
	    					  rw_tff=>rw_tff,
					  	  ui_write_data=>ui_write_data,
 	     				  ui_rw_n=>ui_rw_n_ctlr,
	     				  read_data=>read_data,
	     				  fpga_clk=>fpga_clk_a);

I_databits_inout: DATABITS_INOUT  PORT MAP (
	     				  read_data=>read_data,
	     				  dq=>dq,
	     				  write_data=>write_data,
	     				  rw_tff=>rw_tff,
	     				  fpga_clk=>fpga_clk_a);

I_addrbits_out: ADDRBITS_OUT  PORT MAP ( 
	     			      addr=>addr,
	     			      ui_addr=>ui_addr,
	     			      fpga_clk=>fpga_clk_a);

---------------------------------------------------------------------------------------
-- 读写控制信号直接路由到ZBT SRAM
---------------------------------------------------------------------------------------

	PROCESS(fpga_clk_a) 
BEGIN
		IF (fpga_clk_a 'EVENT AND fpga_clk_a = '1') THEN
			rw_n_p <= ui_rw_n;
		END IF;
	END PROCESS;

I_obuf0: OBUF_F_16  PORT MAP (
I=>rw_n_p, O=>rw_n);

I_tie_unused_sigs: TIE_UNUSED_SIGS  PORT MAP (
	     				    lbo_n=>lbo_n, cke_n=>cke_n, ld_n=>ld_n,
	     				    bwa_n=>bwa_n, bwb_n=>bwb_n, bwc_n=>bwc_n,
	     				    bwd_n=>bwd_n, oe_n=>oe_n, ce_n=>ce_n,
	     				    ce2=>ce2, ce2_n=>ce2_n, zz=>zz);

I_dll_2x_board: DLL_2X_BOARD  PORT MAP (
	     			       clk2x_int=>fpga_clk_a,
	     			       ui_clk_mirror_locked_int=>ui_clk_mirror_locked_int,
	     			       clk2x_ext=>clk,
	     			       ui_clk_mirror_locked_ext=>ui_clk_mirror_locked_ext,
	     			       ui_board_clk=>ui_board_clk,
				           ui_clk_mirror_fb=>ui_clk_mirror_fb);

fpga_clk <= fpga_clk_a;

END RTL;