databits_inout.vhd

VHDL的例子

LIBRARY IEEE;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DATABITS_INOUT IS 
	GENERIC(DATA_BITS : INTEGER := 36);
	PORT(
- DATABITS_INOUT的接口
	     read_data 	: OUT   STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     write_data	: IN	STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     rw_tff		: IN 	STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
	     fpga_clk		: IN 	STD_LOGIC;
--  ZBT SRAM的接口
	     dq			: INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0));
END DATABITS_INOUT;

ARCHITECTURE RTL OF DATABITS_INOUT IS
SIGNAL write_data_p	 : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
SIGNAL rw_tff_p     	 : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);

COMPONENT IOBUF_F_16
	PORT(O : OUT  	STD_LOGIC;
	      IO: INOUT 	STD_LOGIC;
	      I : IN 	STD_LOGIC;
	      T : IN  	STD_LOGIC);
END COMPONENT;

BEGIN

	PROCESS(fpga_clk)
	BEGIN
		IF (fpga_clk 'EVENT AND fpga_clk = '1') THEN
		    FOR i IN 0 TO DATA_BITS-1 LOOP
		      write_data_p(i) <= write_data(i);
		      rw_tff_p(i)    <= rw_tff(i);
            END LOOP;
		END IF;
END PROCESS;


g0:	FOR i IN 0 TO DATA_BITS-1 GENERATE

		iobuf:   IOBUF_F_16 PORT MAP(
O=>read_data(i),
IO=>dq(i),
I=>write_data_p(i),
T=>rw_tff_p(i));
    END GENERATE;
END RTL;