bottom.vhd

VHDL的例子

library IEEE;
use IEEE.STD_Logic_1164.all, 
IEEE.STD_Logic_arith.all,
IEEE.STD_Logic_unsigned.all;

entity EPLD_ENTITY is
    generic (addr_bits: integer := 19); 	-- 地址默认为4M
	port (clk_in: in std_logic;
	      init: in std_logic; 
	      ldc_done: in std_logic;
	      rom_cs: out std_logic;
	      rom_data: in std_logic_vector(7 downto 0);
	      rom_addr: out std_logic_vector(addr_bits-1 downto 0);
	      d_out: out std_logic);
end EPLD_ENTITY;
 

architecture structural of EPLD_ENTITY is
 
component VPCounter
     generic (addr_bits : integer);
     port (clk:  in  	std_logic;
	     init: in 	std_logic;
	     ldc:  in 	std_logic;
           load: out 	std_logic;
	       term_cnt: out std_logic;
           Q :   out 	std_logic_vector(addr_bits-1 downto 0));
end component;

component sr8ps 
    port (D_in :  in 	std_logic_vector(7 downto 0);
	    init :  in 	std_logic;
	    load :  in 	std_logic;
	    CLK :   in 	std_logic;
	    D_out : out 	std_logic  );
end component;


 signal rom_addr_int : std_logic_vector(addr_bits-1 downto 0);
 signal term_cnt_dtct : std_logic;  --地址到达最大地址逻辑为1
 signal load : std_logic;
 signal d_out_buf : std_logic;

begin    
    u1:VPCounter
	generic map (addr_bits => 19)
	port map (clk => clk_in,
		    init => init,
		    ldc => ldc_done,
             load => load,
		    term_cnt => term_cnt_dtct,
		    Q => rom_addr_int);
    u2:sr8ps
	port map (clk => clk_in,
		    d_in => rom_data,
		    load => load,
		    init => init,
		    d_out => d_out_buf);

    -- 当使能和未读完时输出串行数据
d_out <= d_out_buf when (term_cnt_dtct = '0' and ldc_done= '0') else 'Z';

    --从Vpcounte反馈地址计数器到地址输出
rom_addr <= rom_addr_int(addr_bits -1 downto 0);

    -- 不需要时停止
rom_cs <= '1' when (term_cnt_dtct = '1') else '0';     
end structural;-- of VSPROM ;