📄 fifo.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Tx_Sla IS
PORT(
TxSoc : IN STD_LOGIC;
Clock : IN STD_LOGIC; --CLK FROM 8260
Txdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TxAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
TxClav : OUT STD_LOGIC;
TxEnb : IN STD_LOGIC;
In_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
Write_en : OUT STD_LOGIC;
ResetB : IN STD_LOGIC;
Wrclav : IN STD_LOGIC
);
ENDTx_Sla;
ARCHITECTURE RTL OF Tx_Sla IS
SIGNAL TxEnb_tmp : STD_LOGIC;
SIGNAL Byte_Count : STD_LOGIC_VECTOR(4 DOWNTO 0);
TYPE Poll_State_TYPE IS (S0,S1,S2);
SIGNAL Poll_state : Poll_State_TYPE;
SIGNAL Data : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
Justify: --接收轮询地址并验证,如物理地址为0,则发送CLAV
PROCESS(Clock,ResetB)
BEGIN
IF (ResetB = '0') Then --复位逻辑,将状态清零
Poll_state<= S0;
Byte_Count<="00000" ;
Write_en<='0';
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE Poll_state IS
WHEN S0 => -- 如果FIFO内有空间并且轮询地址为0,TXENB为高电平,--送出TXCLAV
IF(TxAddr="00000"and Wrclav='1' ) THEN
IF(TxEnb='1') THEN
TxClav<='1';
Poll_state<= S1;
ELSE
TxClav<='1';
Poll_state<= S0;
END IF;
ELSIF(TxAddr="11111") THEN
TxClav<='Z';
Poll_state<= S0;
ELSE
TxClav<='0';
Poll_state<= S0;
END IF;
WHEN S1 => --如果主设备送出TXSOC则准备接收数据
IF(TxAddr="00000"and Wrclav='1') THEN
TxClav<='1';
ELSIF(TxAddr="11111") THEN
TxClav<='Z';
ELSE
TxClav<='0';
END IF;
IF (TxSoc='1' ) THEN
In_data<= Txdata;
Byte_Count<=Byte_Count+'1';
Write_en<='1';
Poll_state<= S2;
ELSE
Poll_state<= S0;
END IF;
WHEN S2 => 如果接收数据达到帧里的字节数,则停止接收
IF(TxAddr="00000"and Wrclav='1') then
TxClav<='1';
ELSIF(TxAddr="11111") THEN
TxClav<='Z' ;
ELSE
TxClav<='0' ;
END IF;
IF(Byte_Count="11011") THEN
Write_en<='0';
Byte_Count<="00000";
Poll_state<= S0;
ELSE
In_data<= Txdata;
Write_en<='1';
Byte_Count<=Byte_Count+'1';
Poll_state<= S2;
END if;
END CASE;
END IF;
END PROCESS Justify;
END RTL;
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