up.vhd

VHDL的例子

LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY uP IS
		PORT(
		GCLK				: IN  		STD_LOGIC;	
		D	         			: INOUT	STD_LOGIC_VECTOR(1 DOWNTO 0);
      	BA           			: IN  	STD_LOGIC_VECTOR(24 TO 31);
		BCTL0				: IN  	STD_LOGIC;				
		CS6			 		: IN  	STD_LOGIC;
		RESETB				: OUT   STD_LOGIC
         );
END uP;

ARCHITECTURE CTRL OF uP IS

SIGNAL RESET_TMP	: STD_LOGIC;
SIGNAL D_TMP		:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
		
PROCESS(GCLK)
BEGIN
	IF(GCLK'EVENT AND GCLK='1') THEN
	IF (CS6 = '0' AND BCTL0 ='0') THEN
	IF (BA="00000000") THEN
		D_TMP<=D;
		IF (D="10101010") THEN 
			RESET_TMP<='0';
		ELSE
			RESET_TMP<='1';
		END IF;
	ELSE
			RESET_TMP<='1';
	END IF;
	ELSIF(CS6='0' AND BCTL0='1') THEN
	IF (BA="00000000") THEN
		D<=D_TMP;
	END IF;		
	ELSE
	D<="ZZZZZZZZ";
	END IF;

	END IF;
END PROCESS;
	RESETB<= RESET_TMP;    
END CTRL;