dll_mirror_1.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
ENTITY dll_mirror_1 IS
    PORT (CLKIN    : IN  STD_LOGIC;
          CLKFB    : IN  STD_LOGIC;
          CLK0_ext : OUT STD_LOGIC;
          CLK0_int : OUT STD_LOGIC);
END dll_mirror_1;

ARCHITECTURE structural OF dll_mirror_1 IS
COMPONENT IBUFG ………………
COMPONENT CLKDLL…………….
COMPONENT BUFG……………….
COMPONENT OBUF…………………
SIGNAL CLKIN_w, CLKFB_w, CLK0_int_dll, CLK0_int_g, CLK0_ext_dll : STD_LOGIC;
SIGNAL logic0 : STD_LOGIC;
BEGIN 

logic0 <= '0';

clkpad     : IBUFG	PORT MAP  (I=>CLKIN, O=>CLKIN_w);
clkfbpad   : IBUFG  PORT MAP  (I=>CLKFB, O=>CLKFB_w);

dllint 	  : CLKDLL PORT MAP (
CLKIN=>CLKIN_w, 
CLKFB=>CLK0_int_g, 
RST=>logic0,                          
CLK0=>CLK0_int_dll, 
CLK90=>open, 
CLK180=>open, 
CLK270=>open,                          
CLK2X=>open,    
CLKDV=>open, 
LOCKED=>open);

dllext   : CLKDLL PORT MAP (
CLKIN=>CLKIN_w, 
CLKFB=>CLKFB_w, 
RST=>logic0,                          
CLK0=>CLK0_ext_dll, 
CLK90=>open, 
CLK180=>open, 
CLK270=>open,                          
CLK2X=>open,    
CLKDV=>open, 
LOCKED=>open);

clkg      	: BUFG   PORT MAP (I=>CLK0_int_dll, O=>CLK0_int_g);
clkextpad 	: OBUF   PORT MAP (I=>CLK0_ext_dll, O=>CLK0_ext);
CLK0_int <= CLK0_int_g;
END structural;