dll_standard.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
ENTITY dll_standard IS
PORT (

		CLKIN	 	: IN  STD_LOGIC;
		RESET 	 	: IN  STD_LOGIC;
        CLK2X  	: OUT STD_LOGIC;
        CLK4X  	: OUT STD_LOGIC;
        LOCKED		: OUT STD_LOGIC);
END dll_standard;

ARCHITECTURE structural OF dll_standard IS

COMPONENT IBUFG
   GENERIC(
      TimingChecksOn: Boolean 	:= DefaultTimingChecksOn;
      InstancePath: STRING 		:= "*";
      Xon: Boolean 				:= DefaultXon;
      MsgOn: Boolean 			:= DefaultMsgOn;
      tpd_I_O                   	:VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I                    	:VitalDelayType01 := (0.000 ns, 0.000 ns));
   PORT(
      	O                       :OUT   STD_ULOGIC;
      	I                       	:IN    STD_ULOGIC);
END COMPONENT;

COMPONENT IBUF
   GENERIC(
      TimingChecksOn			: Boolean := DefaultTimingChecksOn;
      InstancePath			: STRING := "*";
      Xon: Boolean 			:= DefaultXon;
      MsgOn: Boolean 		:= DefaultMsgOn;
      tpd_I_O                :VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I                  :VitalDelayType01 := (0.000 ns, 0.000 ns));
   PORT(
      	O                    :OUT   STD_ULOGIC;
      	I                     :IN    STD_ULOGIC);
END COMPONENT;

COMPONENT CLKDLL
    GENERIC ( 
    	     	TimingChecksOn 		: Boolean := DefaultTimingChecksOn;
             InstancePath 			: STRING := "*";
             Xon  : Boolean 		:= DefaultXon;
             MsgOn : Boolean 		:= DefaultMsgOn;

             tipd_CLKIN   		: VitalDelayType01 := (0.000 ns, 0.000 ns);
             tipd_CLKFB   		: VitalDelayType01 := (0.000 ns, 0.000 ns);
             tipd_RST     		: VitalDelayType01 := (0.000 ns, 0.000 ns);

             tpd_CLKIN_LOCKED : VitalDelayType01 := (0.100 ns, 0.100 ns);

             tperiod_CLKIN_POSEDGE : VitalDelayType  := 0.010 ns;
             MAXPERCLKIN       	: time := 100 ns;

             tpw_CLKIN_posedge 	: VitalDelayType  := 0.010 ns;
             tpw_CLKIN_negedge 	: VitalDelayType  := 0.010 ns;

             tpw_RST_posedge   	: VitalDelayType  := 0.010 ns;

              DUTY_CYCLE_CORRECTION : Boolean := TRUE;
              CLKDV_DIVIDE : real := 2.0);
PORT (
CLKIN   : IN  STD_ULOGIC := '0';
           CLKFB   : IN  STD_ULOGIC := '0';
           RST     : IN  STD_ULOGIC := '0';
           CLK0    : OUT STD_ULOGIC := '0';
           CLK90   : OUT STD_ULOGIC := '0';
           CLK180  : OUT STD_ULOGIC := '0';
           CLK270  : OUT STD_ULOGIC := '0';
           CLK2X   : OUT STD_ULOGIC := '0';
           CLKDV   : OUT STD_ULOGIC := '0';
           LOCKED  : OUT STD_ULOGIC := '0');
END COMPONENT;
COMPONENT BUFG
   GENERIC(
      TimingChecksOn		: Boolean := DefaultTimingChecksOn;
      InstancePath		: STRING := "*";
      Xon: Boolean 		:= DefaultXon;
      MsgOn: Boolean 	:= DefaultMsgOn;
      tpd_I_O           	:VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I            	:VitalDelayType01 := (0.000 ns, 0.000 ns));
   PORT(
      O                 :OUT   STD_ULOGIC;
      I                 :IN    STD_ULOGIC);
END COMPONENT;
COMPONENT OBUF
   GENERIC(
      TimingChecksOn		: Boolean := DefaultTimingChecksOn;
      InstancePath		: STRING := "*";
      Xon: Boolean 		:= DefaultXon;
      MsgOn: Boolean 	:= DefaultMsgOn;
      tpd_I_O           	:VitalDelayType01 := (0.100 ns, 0.100 ns);
      tipd_I            	:VitalDelayType01 := (0.000 ns, 0.000 ns));
   PORT(
      O                 :OUT   STD_ULOGIC;
      I                 :IN    STD_ULOGIC);
END COMPONENT;

COMPONENT SRL16
  generic (
       TimingChecksOn: Boolean := DefaultTimingChecksOn;
       InstancePath: STRING := "*";
       Xon: Boolean := DefaultXon;
       MsgOn: Boolean := DefaultMsgOn;

       tipd_A0   : VitalDelayType01 := (0.0 ns,  0.0 ns);
       tipd_A1   : VitalDelayType01 := (0.0 ns,  0.0 ns);
       tipd_A2   : VitalDelayType01 := (0.0 ns,  0.0 ns);
       tipd_A3   : VitalDelayType01 := (0.0 ns,  0.0 ns);

       tipd_D    : VitalDelayType01 := (0.0 ns,  0.0 ns);
       tipd_CLK  : VitalDelayType01 := (0.0 ns,  0.0 ns);
--最大的PIN到PIN延迟      
       tpd_A0_Q  : VitalDelayType01 := (0.1 ns, 0.1 ns);
       tpd_A1_Q  : VitalDelayType01 := (0.1 ns, 0.1 ns);
       tpd_A2_Q  : VitalDelayType01 := (0.1 ns, 0.1 ns);
       tpd_A3_Q  : VitalDelayType01 := (0.1 ns, 0.1 ns);
       tpd_CLK_Q : VitalDelayType01 := (0.1 ns, 0.1 ns);

       -- 关于SETUP和HOLD的时延设置
       tsetup_D_CLK_posedge_posedge  : VitalDelayType := 0.01 ns;
       tsetup_D_CLK_negedge_posedge  : VitalDelayType := 0.01 ns;

       thold_D_CLK_posedge_posedge   : VitalDelayType := 0.01 ns;
       thold_D_CLK_negedge_posedge   : VitalDelayType := 0.01 ns;

       -- 最小脉冲宽度
       tpw_CLK_posedge : VitalDelayType := 0.01 ns;
       tpw_CLK_negedge : VitalDelayType := 0.01 ns;

       INIT : bit_vector := X"0000");
  PORT (
  		D   : IN STD_ULOGIC;
        CLK : IN STD_ULOGIC;
        A0  : IN STD_ULOGIC;
        A1  : IN STD_ULOGIC;
        A2  : IN STD_ULOGIC;
        A3  : IN STD_ULOGIC;
        Q   : OUT STD_ULOGIC); 
END COMPONENT;


SIGNAL CLKIN_w, RESET_w, CLK2X_dll, CLK2X_g, CLK4X_dll, CLK4X_g : STD_LOGIC;
SIGNAL LOCKED2X, LOCKED2X_delay, RESET4X, LOCKED4X_dll : STD_LOGIC;
SIGNAL logic1 : STD_LOGIC;

BEGIN 

logic1 <= '1';

clkpad 	: IBUFG  PORT MAP (I=>CLKIN, O=>CLKIN_w);
rstpad 	: IBUF   PORT MAP (I=>RESET, O=>RESET_w);

dll2x 	: CLKDLL PORT MAP (
CLKIN=>CLKIN_w,   
CLKFB=>CLK2X_g,
 RST=>RESET_w,
CLK0=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
CLK2X=>CLK2X_dll,
 CLKDV=>open, 
LOCKED=>LOCKED2X);

clk2xg : BUFG   PORT MAP (I=>CLK2X_dll,   O=>CLK2X_g);

rstsrl : SRL16  PORT MAP (D=>LOCKED2X, CLK=>CLK2X_g, Q=>LOCKED2X_delay,
                          A3=>logic1, A2=>logic1, A1=>logic1, A0=>logic1);

RESET4X <= not LOCKED2X_delay;

dll4x  : CLKDLL PORT MAP (
CLKIN=>CLK2X_g,  
CLKFB=>CLK4X_g, 
RST=>RESET4X,
CLK0=>open,   
CLK90=>open, 
CLK180=>open, 
CLK270=>open,                          
CLK2X=>CLK4X_dll,
CLKDV=>open, 
LOCKED=>LOCKED4X_dll);
clk4xg : BUFG   PORT MAP (I=>CLK4X_dll,  O=>CLK4X_g);
lckpad : OBUF   PORT MAP (I=>LOCKED4X_dll, O=>LOCKED);

CLK2X <= CLK2X_g;
CLK4X <= CLK4X_g;

 END structural;