light.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 light\[5\] light\[5\]~reg0 16.006 ns register " "Info: tco from clock \"clk1\" to destination pin \"light\[5\]\" through register \"light\[5\]~reg0\" is 16.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 11.736 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 11.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk1 1 CLK PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_39; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.555 ns) + CELL(0.935 ns) 5.965 ns clk2 2 REG LC_X23_Y8_N1 2 " "Info: 2: + IC(3.555 ns) + CELL(0.935 ns) = 5.965 ns; Loc. = LC_X23_Y8_N1; Fanout = 2; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.490 ns" { clk1 clk2 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.114 ns) 6.628 ns clk~10 3 COMB LC_X23_Y8_N0 16 " "Info: 3: + IC(0.549 ns) + CELL(0.114 ns) = 6.628 ns; Loc. = LC_X23_Y8_N0; Fanout = 16; COMB Node = 'clk~10'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { clk2 clk~10 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.397 ns) + CELL(0.711 ns) 11.736 ns light\[5\]~reg0 4 REG LC_X23_Y8_N6 5 " "Info: 4: + IC(4.397 ns) + CELL(0.711 ns) = 11.736 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'light\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.108 ns" { clk~10 light[5]~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.235 ns ( 27.56 % ) " "Info: Total cell delay = 3.235 ns ( 27.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.501 ns ( 72.44 % ) " "Info: Total interconnect delay = 8.501 ns ( 72.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 light[5]~reg0 } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.046 ns + Longest register pin " "Info: + Longest register to pin delay is 4.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns light\[5\]~reg0 1 REG LC_X23_Y8_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'light\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { light[5]~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.922 ns) + CELL(2.124 ns) 4.046 ns light\[5\] 2 PIN PIN_91 0 " "Info: 2: + IC(1.922 ns) + CELL(2.124 ns) = 4.046 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'light\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.046 ns" { light[5]~reg0 light[5] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 52.50 % ) " "Info: Total cell delay = 2.124 ns ( 52.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.922 ns ( 47.50 % ) " "Info: Total interconnect delay = 1.922 ns ( 47.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.046 ns" { light[5]~reg0 light[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.046 ns" { light[5]~reg0 light[5] } { 0.000ns 1.922ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 light[5]~reg0 } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.046 ns" { light[5]~reg0 light[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.046 ns" { light[5]~reg0 light[5] } { 0.000ns 1.922ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 12 09:25:18 2008 " "Info: Processing ended: Sat Apr 12 09:25:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}