light.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk2 " "Info: Detected ripple clock \"clk2\" as buffer" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "banner " "Info: Detected ripple clock \"banner\" as buffer" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "banner" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "clk~10 " "Info: Detected gated clock \"clk~10\" as buffer" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register flag\[0\] register light\[5\]~reg0 215.61 MHz 4.638 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 215.61 MHz between source register \"flag\[0\]\" and destination register \"light\[5\]~reg0\" (period= 4.638 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.043 ns + Longest register register " "Info: + Longest register to register delay is 3.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns flag\[0\] 1 REG LC_X25_Y6_N5 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y6_N5; Fanout = 16; REG Node = 'flag\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { flag[0] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.667 ns) + CELL(0.442 ns) 2.109 ns light~2679 2 COMB LC_X23_Y8_N2 1 " "Info: 2: + IC(1.667 ns) + CELL(0.442 ns) = 2.109 ns; Loc. = LC_X23_Y8_N2; Fanout = 1; COMB Node = 'light~2679'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.109 ns" { flag[0] light~2679 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.478 ns) 3.043 ns light\[5\]~reg0 3 REG LC_X23_Y8_N6 5 " "Info: 3: + IC(0.456 ns) + CELL(0.478 ns) = 3.043 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'light\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.934 ns" { light~2679 light[5]~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.920 ns ( 30.23 % ) " "Info: Total cell delay = 0.920 ns ( 30.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.123 ns ( 69.77 % ) " "Info: Total interconnect delay = 2.123 ns ( 69.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.043 ns" { flag[0] light~2679 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.043 ns" { flag[0] light~2679 light[5]~reg0 } { 0.000ns 1.667ns 0.456ns } { 0.000ns 0.442ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.334 ns - Smallest " "Info: - Smallest clock skew is -1.334 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 10.402 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 10.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk1 1 CLK PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_39; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.292 ns) 5.294 ns clk~10 2 COMB LC_X23_Y8_N0 16 " "Info: 2: + IC(3.527 ns) + CELL(0.292 ns) = 5.294 ns; Loc. = LC_X23_Y8_N0; Fanout = 16; COMB Node = 'clk~10'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk1 clk~10 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.397 ns) + CELL(0.711 ns) 10.402 ns light\[5\]~reg0 3 REG LC_X23_Y8_N6 5 " "Info: 3: + IC(4.397 ns) + CELL(0.711 ns) = 10.402 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'light\[5\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.108 ns" { clk~10 light[5]~reg0 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 23.82 % ) " "Info: Total cell delay = 2.478 ns ( 23.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.924 ns ( 76.18 % ) " "Info: Total interconnect delay = 7.924 ns ( 76.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.402 ns" { clk1 clk~10 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.402 ns" { clk1 clk1~out0 clk~10 light[5]~reg0 } { 0.000ns 0.000ns 3.527ns 4.397ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 11.736 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 11.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk1 1 CLK PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_39; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.555 ns) + CELL(0.935 ns) 5.965 ns clk2 2 REG LC_X23_Y8_N1 2 " "Info: 2: + IC(3.555 ns) + CELL(0.935 ns) = 5.965 ns; Loc. = LC_X23_Y8_N1; Fanout = 2; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.490 ns" { clk1 clk2 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.114 ns) 6.628 ns clk~10 3 COMB LC_X23_Y8_N0 16 " "Info: 3: + IC(0.549 ns) + CELL(0.114 ns) = 6.628 ns; Loc. = LC_X23_Y8_N0; Fanout = 16; COMB Node = 'clk~10'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { clk2 clk~10 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.397 ns) + CELL(0.711 ns) 11.736 ns flag\[0\] 4 REG LC_X25_Y6_N5 16 " "Info: 4: + IC(4.397 ns) + CELL(0.711 ns) = 11.736 ns; Loc. = LC_X25_Y6_N5; Fanout = 16; REG Node = 'flag\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.108 ns" { clk~10 flag[0] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.235 ns ( 27.56 % ) " "Info: Total cell delay = 3.235 ns ( 27.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.501 ns ( 72.44 % ) " "Info: Total interconnect delay = 8.501 ns ( 72.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 flag[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 flag[0] } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.402 ns" { clk1 clk~10 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.402 ns" { clk1 clk1~out0 clk~10 light[5]~reg0 } { 0.000ns 0.000ns 3.527ns 4.397ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 flag[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 flag[0] } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.043 ns" { flag[0] light~2679 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.043 ns" { flag[0] light~2679 light[5]~reg0 } { 0.000ns 1.667ns 0.456ns } { 0.000ns 0.442ns 0.478ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.402 ns" { clk1 clk~10 light[5]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.402 ns" { clk1 clk1~out0 clk~10 light[5]~reg0 } { 0.000ns 0.000ns 3.527ns 4.397ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 flag[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 flag[0] } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk1 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk1\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "flag\[1\] flag\[2\] clk1 258 ps " "Info: Found hold time violation between source  pin or register \"flag\[1\]\" and destination pin or register \"flag\[2\]\" for clock \"clk1\" (Hold time is 258 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.334 ns + Largest " "Info: + Largest clock skew is 1.334 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 11.736 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 11.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk1 1 CLK PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_39; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.555 ns) + CELL(0.935 ns) 5.965 ns clk2 2 REG LC_X23_Y8_N1 2 " "Info: 2: + IC(3.555 ns) + CELL(0.935 ns) = 5.965 ns; Loc. = LC_X23_Y8_N1; Fanout = 2; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.490 ns" { clk1 clk2 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.114 ns) 6.628 ns clk~10 3 COMB LC_X23_Y8_N0 16 " "Info: 3: + IC(0.549 ns) + CELL(0.114 ns) = 6.628 ns; Loc. = LC_X23_Y8_N0; Fanout = 16; COMB Node = 'clk~10'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { clk2 clk~10 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.397 ns) + CELL(0.711 ns) 11.736 ns flag\[2\] 4 REG LC_X26_Y6_N7 19 " "Info: 4: + IC(4.397 ns) + CELL(0.711 ns) = 11.736 ns; Loc. = LC_X26_Y6_N7; Fanout = 19; REG Node = 'flag\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.108 ns" { clk~10 flag[2] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.235 ns ( 27.56 % ) " "Info: Total cell delay = 3.235 ns ( 27.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.501 ns ( 72.44 % ) " "Info: Total interconnect delay = 8.501 ns ( 72.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 flag[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 flag[2] } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 10.402 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to source register is 10.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk1 1 CLK PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_39; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.292 ns) 5.294 ns clk~10 2 COMB LC_X23_Y8_N0 16 " "Info: 2: + IC(3.527 ns) + CELL(0.292 ns) = 5.294 ns; Loc. = LC_X23_Y8_N0; Fanout = 16; COMB Node = 'clk~10'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk1 clk~10 } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.397 ns) + CELL(0.711 ns) 10.402 ns flag\[1\] 3 REG LC_X26_Y6_N5 15 " "Info: 3: + IC(4.397 ns) + CELL(0.711 ns) = 10.402 ns; Loc. = LC_X26_Y6_N5; Fanout = 15; REG Node = 'flag\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.108 ns" { clk~10 flag[1] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 23.82 % ) " "Info: Total cell delay = 2.478 ns ( 23.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.924 ns ( 76.18 % ) " "Info: Total interconnect delay = 7.924 ns ( 76.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.402 ns" { clk1 clk~10 flag[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.402 ns" { clk1 clk1~out0 clk~10 flag[1] } { 0.000ns 0.000ns 3.527ns 4.397ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 flag[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 flag[2] } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.402 ns" { clk1 clk~10 flag[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.402 ns" { clk1 clk1~out0 clk~10 flag[1] } { 0.000ns 0.000ns 3.527ns 4.397ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.867 ns - Shortest register register " "Info: - Shortest register to register delay is 0.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns flag\[1\] 1 REG LC_X26_Y6_N5 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y6_N5; Fanout = 15; REG Node = 'flag\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { flag[1] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.309 ns) 0.867 ns flag\[2\] 2 REG LC_X26_Y6_N7 19 " "Info: 2: + IC(0.558 ns) + CELL(0.309 ns) = 0.867 ns; Loc. = LC_X26_Y6_N7; Fanout = 19; REG Node = 'flag\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.867 ns" { flag[1] flag[2] } "NODE_NAME" } } { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 35.64 % ) " "Info: Total cell delay = 0.309 ns ( 35.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 64.36 % ) " "Info: Total interconnect delay = 0.558 ns ( 64.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.867 ns" { flag[1] flag[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.867 ns" { flag[1] flag[2] } { 0.000ns 0.558ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "light.vhd" "" { Text "F:/030501708/light/light.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.736 ns" { clk1 clk2 clk~10 flag[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.736 ns" { clk1 clk1~out0 clk2 clk~10 flag[2] } { 0.000ns 0.000ns 3.555ns 0.549ns 4.397ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.402 ns" { clk1 clk~10 flag[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.402 ns" { clk1 clk1~out0 clk~10 flag[1] } { 0.000ns 0.000ns 3.527ns 4.397ns } { 0.000ns 1.475ns 0.292ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.867 ns" { flag[1] flag[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.867 ns" { flag[1] flag[2] } { 0.000ns 0.558ns } { 0.000ns 0.309ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}