fourbitadder.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 08:38:11 2008 " "Info: Processing started: Thu Apr 10 08:38:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off fourbitadder -c fourbitadder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fourbitadder -c fourbitadder --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "dcin sum\[2\] 14.331 ns Longest " "Info: Longest tpd from source pin \"dcin\" to destination pin \"sum\[2\]\" is 14.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns dcin 1 PIN PIN_144 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_144; Fanout = 2; PIN Node = 'dcin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { dcin } "NODE_NAME" } } { "fourbitadder.vhd" "" { Text "D:/EDA/030501713/adder/fourbitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.431 ns) + CELL(0.590 ns) 7.496 ns onebitadder:U0\|count~74 2 COMB LC_X1_Y9_N3 2 " "Info: 2: + IC(5.431 ns) + CELL(0.590 ns) = 7.496 ns; Loc. = LC_X1_Y9_N3; Fanout = 2; COMB Node = 'onebitadder:U0\|count~74'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.021 ns" { dcin onebitadder:U0|count~74 } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "D:/EDA/030501713/adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.114 ns) 8.048 ns onebitadder:U1\|count~133 3 COMB LC_X1_Y9_N2 2 " "Info: 3: + IC(0.438 ns) + CELL(0.114 ns) = 8.048 ns; Loc. = LC_X1_Y9_N2; Fanout = 2; COMB Node = 'onebitadder:U1\|count~133'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.552 ns" { onebitadder:U0|count~74 onebitadder:U1|count~133 } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "D:/EDA/030501713/adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 8.790 ns onebitadder:U2\|sum 4 COMB LC_X1_Y9_N4 1 " "Info: 4: + IC(0.450 ns) + CELL(0.292 ns) = 8.790 ns; Loc. = LC_X1_Y9_N4; Fanout = 1; COMB Node = 'onebitadder:U2\|sum'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { onebitadder:U1|count~133 onebitadder:U2|sum } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "D:/EDA/030501713/adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.417 ns) + CELL(2.124 ns) 14.331 ns sum\[2\] 5 PIN PIN_97 0 " "Info: 5: + IC(3.417 ns) + CELL(2.124 ns) = 14.331 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'sum\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { onebitadder:U2|sum sum[2] } "NODE_NAME" } } { "fourbitadder.vhd" "" { Text "D:/EDA/030501713/adder/fourbitadder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.595 ns ( 32.06 % ) " "Info: Total cell delay = 4.595 ns ( 32.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.736 ns ( 67.94 % ) " "Info: Total interconnect delay = 9.736 ns ( 67.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.331 ns" { dcin onebitadder:U0|count~74 onebitadder:U1|count~133 onebitadder:U2|sum sum[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.331 ns" { dcin {} dcin~out0 {} onebitadder:U0|count~74 {} onebitadder:U1|count~133 {} onebitadder:U2|sum {} sum[2] {} } { 0.000ns 0.000ns 5.431ns 0.438ns 0.450ns 3.417ns } { 0.000ns 1.475ns 0.590ns 0.114ns 0.292ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 10 08:38:12 2008 " "Info: Processing ended: Thu Apr 10 08:38:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}