prev_cmp_ctime.map.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 09:29:09 2008 " "Info: Processing started: Thu Apr 10 09:29:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ctime -c ctime " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ctime -c ctime" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ctime.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ctime.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ctime-behave " "Info: Found design unit 1: ctime-behave" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ctime " "Info: Found entity 1: ctime" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ctime " "Info: Elaborating entity \"ctime\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ten.vhd 2 1 " "Warning: Using design file ten.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ten-behave " "Info: Found design unit 1: ten-behave" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ten " "Info: Found entity 1: ten" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten ten:U0 " "Info: Elaborating entity \"ten\" for hierarchy \"ten:U0\"" {  } { { "ctime.vhd" "U0" { Text "D:/EDA/030501713/time/ctime.vhd" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a ten.vhd(14) " "Warning (10492): VHDL Process Statement warning at ten.vhd(14): signal \"a\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 14 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a ten.vhd(17) " "Warning (10492): VHDL Process Statement warning at ten.vhd(17): signal \"a\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "a ten.vhd(11) " "Warning (10631): VHDL Process Statement warning at ten.vhd(11): inferring latch(es) for signal or variable \"a\", which holds its previous value in one or more paths through the process" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "cout ten.vhd(11) " "Warning (10631): VHDL Process Statement warning at ten.vhd(11): inferring latch(es) for signal or variable \"cout\", which holds its previous value in one or more paths through the process" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "cout ten.vhd(11) " "Info (10041): Inferred latch for \"cout\" at ten.vhd(11)" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a\[0\] ten.vhd(11) " "Info (10041): Inferred latch for \"a\[0\]\" at ten.vhd(11)" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a\[1\] ten.vhd(11) " "Info (10041): Inferred latch for \"a\[1\]\" at ten.vhd(11)" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a\[2\] ten.vhd(11) " "Info (10041): Inferred latch for \"a\[2\]\" at ten.vhd(11)" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a\[3\] ten.vhd(11) " "Info (10041): Inferred latch for \"a\[3\]\" at ten.vhd(11)" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "six.vhd 2 1 " "Warning: Using design file six.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 six-behave " "Info: Found design unit 1: six-behave" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 six " "Info: Found entity 1: six" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "six six:U1 " "Info: Elaborating entity \"six\" for hierarchy \"six:U1\"" {  } { { "ctime.vhd" "U1" { Text "D:/EDA/030501713/time/ctime.vhd" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b six.vhd(14) " "Warning (10492): VHDL Process Statement warning at six.vhd(14): signal \"b\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 14 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}