prev_cmp_ten.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Info" "ITDB_TH_RESULT" "a\[2\]\$latch reset cin -3.893 ns register " "Info: th for register \"a\[2\]\$latch\" (data pin = \"reset\", clock pin = \"cin\") is -3.893 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin destination 3.280 ns + Longest register " "Info: + Longest clock path from clock \"cin\" to destination register is 3.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.590 ns) 3.280 ns a\[2\]\$latch 2 REG LC_X16_Y12_N3 4 " "Info: 2: + IC(1.221 ns) + CELL(0.590 ns) = 3.280 ns; Loc. = LC_X16_Y12_N3; Fanout = 4; REG Node = 'a\[2\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.811 ns" { cin a[2]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.059 ns ( 62.77 % ) " "Info: Total cell delay = 2.059 ns ( 62.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.221 ns ( 37.23 % ) " "Info: Total interconnect delay = 1.221 ns ( 37.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.280 ns" { cin a[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.280 ns" { cin {} cin~out0 {} a[2]$latch {} } { 0.000ns 0.000ns 1.221ns } { 0.000ns 1.469ns 0.590ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.173 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 CLK PIN_126 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_126; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.110 ns) + CELL(0.292 ns) 6.877 ns a~149 2 COMB LC_X16_Y12_N2 1 " "Info: 2: + IC(5.110 ns) + CELL(0.292 ns) = 6.877 ns; Loc. = LC_X16_Y12_N2; Fanout = 1; COMB Node = 'a~149'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.402 ns" { reset a~149 } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 7.173 ns a\[2\]\$latch 3 REG LC_X16_Y12_N3 4 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 7.173 ns; Loc. = LC_X16_Y12_N3; Fanout = 4; REG Node = 'a\[2\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { a~149 a[2]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.881 ns ( 26.22 % ) " "Info: Total cell delay = 1.881 ns ( 26.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.292 ns ( 73.78 % ) " "Info: Total interconnect delay = 5.292 ns ( 73.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.173 ns" { reset a~149 a[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.173 ns" { reset {} reset~out0 {} a~149 {} a[2]$latch {} } { 0.000ns 0.000ns 5.110ns 0.182ns } { 0.000ns 1.475ns 0.292ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.280 ns" { cin a[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.280 ns" { cin {} cin~out0 {} a[2]$latch {} } { 0.000ns 0.000ns 1.221ns } { 0.000ns 1.469ns 0.590ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.173 ns" { reset a~149 a[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.173 ns" { reset {} reset~out0 {} a~149 {} a[2]$latch {} } { 0.000ns 0.000ns 5.110ns 0.182ns } { 0.000ns 1.475ns 0.292ns 0.114ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 7 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 23:43:13 2008 " "Info: Processing ended: Wed Apr 09 23:43:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}