prev_cmp_ten.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "cin " "Info: Assuming node \"cin\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "reset " "Info: Assuming node \"reset\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cin register a\[3\]\$latch register a\[0\]\$latch 218.96 MHz 4.567 ns Internal " "Info: Clock \"cin\" has Internal fmax of 218.96 MHz between source register \"a\[3\]\$latch\" and destination register \"a\[0\]\$latch\" (period= 4.567 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.912 ns + Longest register register " "Info: + Longest register to register delay is 2.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[3\]\$latch 1 REG LC_X16_Y12_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y12_N4; Fanout = 3; REG Node = 'a\[3\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[3]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.114 ns) 1.269 ns Equal0~30 2 COMB LC_X16_Y12_N7 5 " "Info: 2: + IC(1.155 ns) + CELL(0.114 ns) = 1.269 ns; Loc. = LC_X16_Y12_N7; Fanout = 5; COMB Node = 'Equal0~30'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.269 ns" { a[3]$latch Equal0~30 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.292 ns) 2.043 ns a~147 3 COMB LC_X16_Y12_N0 1 " "Info: 3: + IC(0.482 ns) + CELL(0.292 ns) = 2.043 ns; Loc. = LC_X16_Y12_N0; Fanout = 1; COMB Node = 'a~147'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.774 ns" { Equal0~30 a~147 } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.442 ns) 2.912 ns a\[0\]\$latch 4 REG LC_X16_Y12_N1 5 " "Info: 4: + IC(0.427 ns) + CELL(0.442 ns) = 2.912 ns; Loc. = LC_X16_Y12_N1; Fanout = 5; REG Node = 'a\[0\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { a~147 a[0]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.848 ns ( 29.12 % ) " "Info: Total cell delay = 0.848 ns ( 29.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.064 ns ( 70.88 % ) " "Info: Total interconnect delay = 2.064 ns ( 70.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.912 ns" { a[3]$latch Equal0~30 a~147 a[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.912 ns" { a[3]$latch {} Equal0~30 {} a~147 {} a[0]$latch {} } { 0.000ns 1.155ns 0.482ns 0.427ns } { 0.000ns 0.114ns 0.292ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.485 ns - Smallest " "Info: - Smallest clock skew is -0.485 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin destination 2.794 ns + Shortest register " "Info: + Shortest clock path from clock \"cin\" to destination register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.114 ns) 2.794 ns a\[0\]\$latch 2 REG LC_X16_Y12_N1 5 " "Info: 2: + IC(1.211 ns) + CELL(0.114 ns) = 2.794 ns; Loc. = LC_X16_Y12_N1; Fanout = 5; REG Node = 'a\[0\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { cin a[0]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 56.66 % ) " "Info: Total cell delay = 1.583 ns ( 56.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.211 ns ( 43.34 % ) " "Info: Total interconnect delay = 1.211 ns ( 43.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { cin a[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { cin {} cin~out0 {} a[0]$latch {} } { 0.000ns 0.000ns 1.211ns } { 0.000ns 1.469ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin source 3.279 ns - Longest register " "Info: - Longest clock path from clock \"cin\" to source register is 3.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.590 ns) 3.279 ns a\[3\]\$latch 2 REG LC_X16_Y12_N4 3 " "Info: 2: + IC(1.220 ns) + CELL(0.590 ns) = 3.279 ns; Loc. = LC_X16_Y12_N4; Fanout = 3; REG Node = 'a\[3\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { cin a[3]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.059 ns ( 62.79 % ) " "Info: Total cell delay = 2.059 ns ( 62.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.220 ns ( 37.21 % ) " "Info: Total interconnect delay = 1.220 ns ( 37.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.279 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.279 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.220ns } { 0.000ns 1.469ns 0.590ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { cin a[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { cin {} cin~out0 {} a[0]$latch {} } { 0.000ns 0.000ns 1.211ns } { 0.000ns 1.469ns 0.114ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.279 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.279 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.220ns } { 0.000ns 1.469ns 0.590ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.170 ns + " "Info: + Micro setup delay of destination is 1.170 ns" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.912 ns" { a[3]$latch Equal0~30 a~147 a[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.912 ns" { a[3]$latch {} Equal0~30 {} a~147 {} a[0]$latch {} } { 0.000ns 1.155ns 0.482ns 0.427ns } { 0.000ns 0.114ns 0.292ns 0.442ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { cin a[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { cin {} cin~out0 {} a[0]$latch {} } { 0.000ns 0.000ns 1.211ns } { 0.000ns 1.469ns 0.114ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.279 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.279 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.220ns } { 0.000ns 1.469ns 0.590ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "a\[3\]\$latch reset cin 6.230 ns register " "Info: tsu for register \"a\[3\]\$latch\" (data pin = \"reset\", clock pin = \"cin\") is 6.230 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.184 ns + Longest pin register " "Info: + Longest pin to register delay is 8.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 CLK PIN_126 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_126; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.116 ns) + CELL(0.292 ns) 6.883 ns a~150 2 COMB LC_X16_Y12_N8 1 " "Info: 2: + IC(5.116 ns) + CELL(0.292 ns) = 6.883 ns; Loc. = LC_X16_Y12_N8; Fanout = 1; COMB Node = 'a~150'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.408 ns" { reset a~150 } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 7.618 ns a~151 3 COMB LC_X16_Y12_N5 1 " "Info: 3: + IC(0.443 ns) + CELL(0.292 ns) = 7.618 ns; Loc. = LC_X16_Y12_N5; Fanout = 1; COMB Node = 'a~151'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { a~150 a~151 } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.114 ns) 8.184 ns a\[3\]\$latch 4 REG LC_X16_Y12_N4 3 " "Info: 4: + IC(0.452 ns) + CELL(0.114 ns) = 8.184 ns; Loc. = LC_X16_Y12_N4; Fanout = 3; REG Node = 'a\[3\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { a~151 a[3]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 26.55 % ) " "Info: Total cell delay = 2.173 ns ( 26.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.011 ns ( 73.45 % ) " "Info: Total interconnect delay = 6.011 ns ( 73.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.184 ns" { reset a~150 a~151 a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.184 ns" { reset {} reset~out0 {} a~150 {} a~151 {} a[3]$latch {} } { 0.000ns 0.000ns 5.116ns 0.443ns 0.452ns } { 0.000ns 1.475ns 0.292ns 0.292ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.325 ns + " "Info: + Micro setup delay of destination is 1.325 ns" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin destination 3.279 ns - Shortest register " "Info: - Shortest clock path from clock \"cin\" to destination register is 3.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.590 ns) 3.279 ns a\[3\]\$latch 2 REG LC_X16_Y12_N4 3 " "Info: 2: + IC(1.220 ns) + CELL(0.590 ns) = 3.279 ns; Loc. = LC_X16_Y12_N4; Fanout = 3; REG Node = 'a\[3\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { cin a[3]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.059 ns ( 62.79 % ) " "Info: Total cell delay = 2.059 ns ( 62.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.220 ns ( 37.21 % ) " "Info: Total interconnect delay = 1.220 ns ( 37.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.279 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.279 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.220ns } { 0.000ns 1.469ns 0.590ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.184 ns" { reset a~150 a~151 a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.184 ns" { reset {} reset~out0 {} a~150 {} a~151 {} a[3]$latch {} } { 0.000ns 0.000ns 5.116ns 0.443ns 0.452ns } { 0.000ns 1.475ns 0.292ns 0.292ns 0.114ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.279 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.279 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.220ns } { 0.000ns 1.469ns 0.590ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cin a\[1\] a\[1\]\$latch 8.258 ns register " "Info: tco from clock \"cin\" to destination pin \"a\[1\]\" through register \"a\[1\]\$latch\" is 8.258 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin source 2.790 ns + Longest register " "Info: + Longest clock path from clock \"cin\" to source register is 2.790 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.114 ns) 2.790 ns a\[1\]\$latch 2 REG LC_X16_Y12_N9 4 " "Info: 2: + IC(1.207 ns) + CELL(0.114 ns) = 2.790 ns; Loc. = LC_X16_Y12_N9; Fanout = 4; REG Node = 'a\[1\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { cin a[1]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 56.74 % ) " "Info: Total cell delay = 1.583 ns ( 56.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.207 ns ( 43.26 % ) " "Info: Total interconnect delay = 1.207 ns ( 43.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.790 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.790 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.207ns } { 0.000ns 1.469ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.468 ns + Longest register pin " "Info: + Longest register to pin delay is 5.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[1\]\$latch 1 REG LC_X16_Y12_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y12_N9; Fanout = 4; REG Node = 'a\[1\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[1]$latch } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.344 ns) + CELL(2.124 ns) 5.468 ns a\[1\] 2 PIN PIN_26 0 " "Info: 2: + IC(3.344 ns) + CELL(2.124 ns) = 5.468 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'a\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.468 ns" { a[1]$latch a[1] } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 38.84 % ) " "Info: Total cell delay = 2.124 ns ( 38.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.344 ns ( 61.16 % ) " "Info: Total interconnect delay = 3.344 ns ( 61.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.468 ns" { a[1]$latch a[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.468 ns" { a[1]$latch {} a[1] {} } { 0.000ns 3.344ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.790 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.790 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.207ns } { 0.000ns 1.469ns 0.114ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.468 ns" { a[1]$latch a[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.468 ns" { a[1]$latch {} a[1] {} } { 0.000ns 3.344ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}