prev_cmp_ctime.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Info" "ITDB_FULL_TCO_RESULT" "clk a7\[0\] six:U5\|b\[0\]\$latch 20.902 ns register " "Info: tco from clock \"clk\" to destination pin \"a7\[0\]\" through register \"six:U5\|b\[0\]\$latch\" is 20.902 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.214 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 14.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.935 ns) 4.388 ns set 2 REG LC_X8_Y8_N1 33 " "Info: 2: + IC(1.984 ns) + CELL(0.935 ns) = 4.388 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.919 ns" { clk set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.671 ns) + CELL(0.292 ns) 9.351 ns ten:U4\|cout 3 REG LC_X8_Y8_N4 4 " "Info: 3: + IC(4.671 ns) + CELL(0.292 ns) = 9.351 ns; Loc. = LC_X8_Y8_N4; Fanout = 4; REG Node = 'ten:U4\|cout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.963 ns" { set ten:U4|cout } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.571 ns) + CELL(0.292 ns) 14.214 ns six:U5\|b\[0\]\$latch 4 REG LC_X9_Y8_N3 11 " "Info: 4: + IC(4.571 ns) + CELL(0.292 ns) = 14.214 ns; Loc. = LC_X9_Y8_N3; Fanout = 11; REG Node = 'six:U5\|b\[0\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.863 ns" { ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.988 ns ( 21.02 % ) " "Info: Total cell delay = 2.988 ns ( 21.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.226 ns ( 78.98 % ) " "Info: Total interconnect delay = 11.226 ns ( 78.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.214 ns" { clk set ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.214 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[0]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.571ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.688 ns + Longest register pin " "Info: + Longest register to pin delay is 6.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns six:U5\|b\[0\]\$latch 1 REG LC_X9_Y8_N3 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y8_N3; Fanout = 11; REG Node = 'six:U5\|b\[0\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { six:U5|b[0]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.172 ns) + CELL(0.590 ns) 1.762 ns decoder:X7\|Mux6~19 2 COMB LC_X9_Y8_N1 1 " "Info: 2: + IC(1.172 ns) + CELL(0.590 ns) = 1.762 ns; Loc. = LC_X9_Y8_N1; Fanout = 1; COMB Node = 'decoder:X7\|Mux6~19'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.762 ns" { six:U5|b[0]$latch decoder:X7|Mux6~19 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/EDA/030501713/time/decoder.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.802 ns) + CELL(2.124 ns) 6.688 ns a7\[0\] 3 PIN PIN_96 0 " "Info: 3: + IC(2.802 ns) + CELL(2.124 ns) = 6.688 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'a7\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.926 ns" { decoder:X7|Mux6~19 a7[0] } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns ( 40.58 % ) " "Info: Total cell delay = 2.714 ns ( 40.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.974 ns ( 59.42 % ) " "Info: Total interconnect delay = 3.974 ns ( 59.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.688 ns" { six:U5|b[0]$latch decoder:X7|Mux6~19 a7[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.688 ns" { six:U5|b[0]$latch {} decoder:X7|Mux6~19 {} a7[0] {} } { 0.000ns 1.172ns 2.802ns } { 0.000ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.214 ns" { clk set ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.214 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[0]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.571ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.688 ns" { six:U5|b[0]$latch decoder:X7|Mux6~19 a7[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.688 ns" { six:U5|b[0]$latch {} decoder:X7|Mux6~19 {} a7[0] {} } { 0.000ns 1.172ns 2.802ns } { 0.000ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 37 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 37 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 10 09:29:26 2008 " "Info: Processing ended: Thu Apr 10 09:29:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}